Verilog output value X in Gate Level - simulation

Question

I'm trying to make a counter that counts up to 18 and from there it needs to go back to 0. I designed it with using D-flip flops, I calculated the functions using K-Map and tried to implement that design in Gate Level in ISE Design Suite.
But when I try to test it in Simulation, all values except clock is always X. I don't know what it means and how can I overcome that.
Here is my code:
module denemeff(A, B, C, D, E, C_CLK);
output A, B, C, D, E;
input C_CLK; // C_CLK stands for Common Clock.
wire C_CLK;
wire A, B, C, D, E;
wire A_BAR, B_BAR, C_BAR, D_BAR, E_BAR;
wire Da, Db, Dc, Dd, De;
wire Da_1, Da_2, Db_1, Db_2, Db_3, Dc_1, Dc_2, Dc_3, Dd_1, Dd_2, Dd_3, De_1, De_2;
not notA(A_BAR, A);
not notB(B_BAR, B);
not notC(C_BAR, C);
not notD(D_BAR, D);
not notE(E_BAR, E);
//Operations for Da
and Da_and_1(Da_1, A_BAR, B, C, D, E);
and Da_and_2(Da_2, A, B_BAR, C_BAR, D_BAR);
or Da_final(Da, Da_1, Da_2);
//Operations for Db
and Db_and_1(Db_1, A_BAR, B, E_BAR);
and Db_and_2(Db_2, A_BAR, B, D_BAR);
and Db_and_3(Db_3, A_BAR, B, C_BAR);
or Db_final(Db, Db_1, Db_2, Db_3);
//Operations for Dc
and Dc_and_1(Dc_1, A_BAR, C_BAR, D, E);
and Dc_and_2(Dc_2, A_BAR, C, D_BAR);
and Dc_and_3(Dc_3, A_BAR, C, E_BAR);
or Dc_final(Dc, Dc_1, Dc_2, Dc_3);
//Operations for Dd
and Dd_and_1(Dd_1, B_BAR, C_BAR, D_BAR, E);
and Dd_and_2(Dd_2, A_BAR, D_BAR, E);
and Dd_and_3(Dd_3, A_BAR, D, E_BAR);
or Dd_final(Dd, Dd_1, Dd_2, Dd_3);
//Operations for De
and De_and_1(De_1, A_BAR, E_BAR);
and De_and_2(De_2, B_BAR, C_BAR, D_BAR, E_BAR);
or De_final(De, De_1, De_2);
dff d_ff_a(A, A_BAR, Da, C_CLK);
dff d_ff_b(B, B_BAR, Db, C_CLK);
dff d_ff_c(C, C_BAR, Dc, C_CLK);
dff d_ff_d(D, D_BAR, Dd, C_CLK);
dff d_ff_e(E, E_BAR, De, C_CLK);
endmodule
module dff(Q, Q_BAR, D, CLK);
input D, CLK;
output Q, Q_BAR;
wire D, CLK;
wire Q, Q_BAR;
not not1(D_BAR, D);
nand n1(X, D, CLK);
nand n2(Y, D_BAR, CLK);
nand n3(Q, Q_BAR, X);
nand n4(Q_BAR, Q, Y);
endmodule

Answer 1

You need to reset your flops. With your current DFF description, the initial output value of Q is unknown and there is no way to reset it to a known value. Hence you see the x values.
See here for some NAND-based DFF designs with asynchronous resets:
http://userpages.umbc.edu/~squire/cs313_l22.html
Or just define them behaviorally:
http://www.asic-world.com/examples/verilog/d_ff.html