Reading wrong data when indexing a nested array - system-verilog

Question

I'm implementing a dcache in a pipeline processor.
My dcache is a 2-way associative with 2 words per block and 8 indexes
This is how I initialized my cache structure.
typedef struct packed {
logic [25:0] tag;
logic valid, dirty;
word_t [1:0] data;
} block_t;
typedef struct packed {
block_t [1:0] way;
} dcache_t;
dcache_t [7:0] cache;
So to access a word: cache[i].way[j].data[k]
I can write to cache fine.
index, way and sel are variables that use combination logic to determine where to index.
So for example, this line is in my always_ff register for the cache.
cache[index].way[way].data[sel] = ccif.dload[CPUID];
After the above line of code, the following gets stored into cache
for index = 6, way = 0, sel = 0
cache[6].way[0].data[0] <== 0x01234567
and after the next clock cycle the following for index = 6, way = 0, sel = 1
cache[6].way[0].data[1] <== 0x89ABCDEF
Since I load two words at a time.
...but when I read from it using index = 6, way = 0, sel = 1
dcif.dmemload = cache[index].way[way].data[sel];
The following gets read from my cache
dcif.dmemload <== 0xCDEF0123
I get wrong value and don't know why, since the value in cache is still the same and hasn't changed.
This is the current state of a section of my cache at the time of reading
+-------+------------+------------+
| index | data[1] | data[0] |
+-------+------------+------------+
| 6 | 89ABCDEF | 01234567 |
+-------+------------+------------+
Any ideas? I'm confused because my indexing works fine when writing but something weird happens when reading
Edit: the value read isn't always offset by 2 bytes.
I'm not sure if I have too many nested arrays.

Answer 1

This is a bug in ModelSim/Questa that is fixed in the next release.
The solution is to not make the entire nested array all packed. You probably did not mean to have your cache packed anyways. You should not pack your arrays unless you need to access the whole array as a single integral value.
dcache_t cache[7:0];