VHDL macro for vector indices - macros

Question

I am searching for a macro, constant or attribute, whatever it is, replaces "(x downto y)". To explain in detail for example complex numbers,
there is a generic value WIDTH,
signal num : std_logic_vector(2*WIDTH downto 0);
**pseudo**
re = 2*WIDTH-1 downto WIDTH;
im = WIDTH-1 downto 0;
**pseudo**
x <= num(re);
y <= num(im); etc
also it could be some attribute like range. eg
x <= num(num're);
y <= num(num'im);
I use it a lot and it should be great for better readability and writing clean code

Answer 1

A subtype can be used to declare an integer range like:
-- **pseudo** re = 2*WIDTH-1 downto WIDTH; im = WIDTH-1 downto 0; **pseudo**
subtype re is natural range 2*WIDTH-1 downto WIDTH;
subtype im is natural range WIDTH-1 downto 0;
Then it is possible to do:
x <= num(re);
y <= num(im);
With x and y declared as std_logic_vector(WIDTH-1 downto 0), or std_logic_vector(re) and std_logic_vector(im).
Btw. num should probably have highest index as 2*WIDTH-1, and not 2*WIDTH (off-by-one error).

Answer 2

Maybe not exactly what you had in mind, but a VHDL record would seem to be a good fit for what you are trying to do.
You define your record type:
type mycomplex_t is record
re : std_logic_vector(WIDTH-1 downto 0);
im : std_logic_vector(WIDTH-1 downto 0);
end record;
Then, you declare your signal to be of this type:
signal num : mycomplex_t;
And you use it as such:
x <= num.re;
y <= num.im;
You can also assign it like this :
num <= (re => x2, im => y2);
Or, like this:
num.re <= x2;
num.im <= y2;
Or all at once from another signal of the same type:
signal other_complex : mycomplex_t;
-- (...)
num <= other_complex;