I've been reading through UVM: illegal combination of driver and procedural assignment warning and paper attached in answer.
(Please consider paper linked in the question mentioned)
However drivers are implemented to drive reset values on interface signals instead of on clocking block signals, the clock is not guaranteed to be running at reset.
So how can I go about this scenario if interface signals are declared wires.
for e.g.
consider the code in linked question. General scenario would be
#(vif.cb);
vif.cb.opcode <= value;
This is correct even if opcode is declared net in interface cause clocking block will take care of correct assignment. However I can't say
#(vif.rst);
vif.cb.opcode <= init_value;
since I can't guarantee clock at reset. To accommodate this I'll have to change clock generation strategy.
Neither can I say
vif.opcode <= init_value;
cause its illegal to use procedural assignment with net type signals
The other way is gating signals declared as net with reset but I think for that I'll have to declare temporary signals in interface. Can anyone elaborate how can I achieve driving nets at reset ?
While it's illegal to assign nets from procedural code, it's legal to force values onto them. You can do the following:
#(negedge vif.rst);
force vif.opcode = 0;
Bonus: IMO you shouldn't have opcode defined as a wire. The illegal combination of procedural and continuous driver warning is wrong. The SV 2012 standard clearly states in 14.16.2 Driving clocking output signals:
It is possible to use a procedural assignment to assign to a signal associated with an output clockvar. When
the associated signal is a variable, the procedural assignment assigns a new value to the variable, and the
variable shall hold that value until another assignment occurs (either from a drive to a clocking block output
or another procedural assignment).
Related
What is a test point and its intended use in matlab ?
I am working on a model and have to use 3 AND gates in conjunction coupled with similar 2 more AND gates. While checking the model I am getting warning "Identify single logical operator blocks with more than 9 inputs signals.", which is not shown if I use testpoint on each of these AND gate output.
Think of a signal in Simulink as corresponding to a memory location.
In an effort to reduce memory consumption, one of the standard optimizations used by Simulink is to re-use the same memory address when possible.
For instance, assume the input to a gain block is stored at memory location X. Then the output of the gain block would overwrite the data in X. Consequently the input value would no longer be available. But it doesn't need to be as it's value is never used again. (This assumes that the input value is not used elsewhere, such as feeding a block like a Scope.)
In your case, the warning is telling you something about Simulink storing the logical values in memory locations that it subsequently overwrites when possible.
Note that Simulink will never re-use memory when it needs the signal value in subsequent calculations, i.e. when it would effect the simulation result if it did so.
Nor will it re-use memory (for a specific signal) when you designate the signal as being a test point.
This is why the warning is going away in your case.
One particular use of a test point is if you are using a Floating Scope. Floating Scopes cannot be made to look at signals where the memory is being re-used because then it wouldn't be clear which signal was being displaying.
By looking at only test points it is guaranteed that you are looking at the expected data/memory.
I want to feed the initial conditions in state space matrix block in simulink by using signals "from-go to signal blocks". I m trying it with signal blocks but some errors pop up at the end and it says that the signal variables used as initial conditions are all undefined variable. In other words there exists "Undefined function or variable".
Any help appreciated, thank you
I take it you are using the State-Space block. The "initial conditions" parameter for the block is just that, a parameter:
You need to understand the difference between a parameter and a signal: a parameter is something that is constant throughout the simulation (e.g. a variable in the MATLAB workspace), whereas a signal is something whose value is updated at each time step. You cannot use a "signal" to parameterise a block, it's not possible, you can only use a parameter. Hope that clears things up.
If I misunderstood your question, please provide more details, including which block(s) you are using and if possible a screenshot of the model and the relevant block parameters.
Variables in testbench mostly are instantiated as bit rather than reg. But bit is just 2 state variable (0 and 1), reg is 4 state variable (0,1,x and z). Why people used bit as testbench variables? I took over an old project and all the testbench variables were bit. So when the checker perform checks like
if (data_rtl === data_expected) // reg[63:0] data_rtl, bit[63:0] data_expected
I couldn't perform X check on the data_expected side. Certainly it's common to use bit, why people are doing this? What's the advantage of bit over reg in systemverilog ?
Generally, there no need for 4-state types in the stimulus generation and prediction components of your testbench. Two-state simulation has the benefit of less memory overhead, which effectively doubles the size of your data caches. You basically just need to check for X's at the proper time in the interface between the testbench and DUT.
The generation and propagation of X's in a design is a broad topic in itself. Most simulations are grossly inaccurate in either being too optimistic or too pessimistic when it comes to X's in different areas of your design. Sometimes, it's better to use static analysis (timing or formal) tools in these situation.
To a certain extent you answered your own question. bit is a two-state variable. For a lot of verification testbench applications, x and z values are not necessary. The computational/memory overhead of the extra two states, as well as the additional concern about the possibility of the variable being set to z, or x, aren't needed, and so aren't used.
There are some a key difference in bit & reg
reg is a 4 State Variable (1 or 0 or X or Z, with default X), but bit is a 2 State Variable (0 or 1, with default 0)
Now what does that effect to us.
4 State variables, are necessary for hardware, as in hardware, depending upon voltage level & driver of a wire, a wire can have logical value 1 or 0 or X or Z. So for hardware point of view, reg should be used.
But for stimulus point of view, often we do not require X or Z state, as you would never drive a wire with unknown (X), or without any driver (Z). So in that case, bit can be used, as bit contains only 2 states.
Hope you would have got the difference
I substituted my originial question, the problem is still the same, but the conditions are now different. To review the original question, have a look at the revisions.
I'm looking for a way to interactively select the signals I want to get displayed in my scope Block. The Bus Selector Block with the property Output as Bus does exactly that. I can select all desired signals conveniently without changing any block or signal dimensions.
But the scope block can obviously not handle properly signal names of buses. Therefore my scope legends are wrong:
If I don't set the Output as Bus property and Mux the signal together into the scope block it displays the right signal names. But this is no option as I'd need to adjust the Mux-dimension according to the signals selected.
Are there any workarounds?
(A Floating Scope is no option either)
I am trying to find more information on making a custom PID block in MATLAB. I have most of it done but there are a few parameters that I don't really understand and as such I don't know what value to give them. NOTE I am NOT asking for help tuning PID gains.
They are all inside the filter coefficient block:
When I open the block I have to set a few parameters (output min/max, data type, parameter min/max, etc.). Can someone explain to me what these mean? I can't find good resources anywhere. The only thing that I've tried which works is setting each to [] (i.e. -inf) and the input/output data types to 'Inherit: Inherit via internal rule' but then my output goes to hell. If I copy paste the blocks from the PID block there are a bunch of variables which I haven't defined anywhere so the program won't even compile.
Can someone point out some good resources for this or else explain it? Thanks!
You should get your blocks from the standard Simulink library, not from under the PID block mask. The ones under the mask have been set-up to use variables that are passed from/through the mask, which you are not doing.
The block you have circled is just a gain block (from the Math library).
You most likely won't need to make any changes to the default settings of the block other than the constant value (which needs to be the N that you want to use in the approximation of the derivative term in your controller).
To answer your specific question about what the parameters are, some of them are used to specify data types (if you don't want to use the default double precision), some are only used in code generation, some others only for other specific tasks.
All of them are described (in more, or sometimes less, detail) in the doc for the block, obtained by pressing the help button on the block's dialog.