below is the code snippet of my top_file
`define NUM_SENSORS 2;
module test_top();
svt_configuration multiple_top_cfg[`NUM_SENSORS]; // configuration class instance
svt_xmtr_if xmtr_if[`NUM_OF_SENSORS](); // interface instance
svt_rcvr_if rcvr_if[`NUM_OF_SENSORS]();
always begin
fork
change_clock_speed();
join_none
end
task automatic change_clock_speed();
for(i=0; i<`NUM_OF_SENSORS; i++) begin
wait(multiple_top_cfg[i] != null);
#(multiple_new_dphy_ui[i]) begin
if(multiple_top_cfg[i].xmtr_cfg.lane_cfg.clock_type == svt_mipi_lane_configuration::NON_CONTINUOUS) begin
wait({xmtr_if[i].serial_if.serial_tx_clk_if.dp,xmtr_if[i].serial_if.serial_tx_clk_if.dn} === 2'b11);
end
else begin
if(multiple_top_cfg[i].xmtr_cfg.lane_cfg.clock_type == svt_mipi_lane_configuration::CONTINUOUS) begin
wait({xmtr_if[i].serial_if.serial_if[0].dp,xmtr_if[i].serial_if.serial_if[0].dn} === 2'b11);
end
end
multiple_change_dphy_ui[i] = 1; // this is a local reg
multiple_tx_clock_period[i] = multiple_new_dphy_ui[i]; // this is a local reg
multiple_quadrature[i] = multiple_new_dphy_ui[i]; // this is a local reg
end
end
endtask
// ... other lines
endmodule
When i am running my test, i am getting this error :
Error-[IIXMR] Invalid index in cross-module reference
top.serial.sv, 311
Invalid index in cross-module reference due to index is not constant.
Argument: xmtr_if[i].serial_if.serial_tx_clk_if.dp
Source info: : wait (({xmtr_if[i].serial_if.serial_tx_clk_if.dp,
xmtr_if[i].serial_if.serial_tx_clk_if.dn} === 2'b11))
I understand why this error is coming, but i don't have any solution to it... can any one help...
I tried to put the always block inside generate block. But another error is coming.
Any solution to this error please...
Thanks,
Biren
I have found a solution it. What i did is :
genvar i;
generate
for(i=0; i<`NUM_SENSORS; i++) begin
always begin
change_clock_speed();
end
end
endgenerate
Now it's working. :)
Related
Can $urandom be NBA assigned in a for loop to an unpacked array of variables?
module tb();
logic clk [2];
initial clk[0] = 0;
always clk[0] = #1ns !clk[0];
for (genvar i = 1; i < 2; i++)
assign #(1ns/2) clk[i] = clk[i-1];
int tmp [2] [8];
always # (posedge clk[0]) begin
foreach (tmp[0][i]) begin
/*int m;
m = $urandom(); // SECTION 1 - using this code works (commenting out SECTION 2)
tmp[0][i] <= m;*/
tmp[0][i] <= $urandom(); // SECTION 2
end
#1ns;
foreach (tmp[0][i]) begin
$display("%1d", tmp[0][i]);
end
$finish();
end
for (genvar i = 1; i < 2; i++) begin
always_ff # (posedge clk[i]) begin
tmp[i] <= tmp[i-1]; // SECTION 3 (just removing this works too)
end
end
endmodule
Using Cadence tools (xrun 17.09-v002), I get all 8 of tmp[0] ints assigned the same value.
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Can someone confirm whether this code is legal?
I have spoken to Cadence and been told this:
R&D’s response.
This use model of having $urandom call inside a non-blocking assignment is wrong.
The scheduling semantics of System Verilog dictates that the RHS is calculated and sampled once in the "inactive region" and then in the "NBA region" it's assigned the ALL of the elements of the foreach at the same time!
There is no difference in calling $urandom in a procedural loop versus serially calling $urandom multiple times. Your code gives the desired results in several tools, including Cadence's on EDAPlayground.com. Perhaps you are not showing is part of your problem. It always helps to show an MCVE, like
module top;
int tmp [2] [8];
bit clk;
initial begin
#1 clk=1;
#1 $display("%p",
tmp[0]);
end
always # (posedge clk) begin
foreach (tmp[,i]) begin
tmp[0][i] <= $urandom();
end
end
endmodule
I am trying to assign value on a specific bit of a 2D array(code[i][k]). This is a net type. But the value not being assigned.reg [3:0] code[0:3] gets unknown logic value 'X'.
Here is the code snippet
for(k=0;k<len;k++) begin
if (tc[k] == 1'b0) begin
code[i][k]= 1'b0;//----> value is not assigning as expected
end else begin
code[i][k]= 1'b1;// ---> value is not assigning as expected
end
end
codeLen[i] = len;
This for loop belongs to always block.Here, code and codeLen is output type.
output [3:0] code[0:3];
output [3:0] codeLen[0:3];
reg [3:0] code[0:3];
reg [3:0] codeLen[0:3];
codeLen[i] is assigned correctly but not the code[i][k]. I was trying to assign k-th bit of i-th byte.
Details
I have created a module which takes 6 inputs and returns two 2-dimensional arrays as output.
Here is the module:
`timescale 1ns / 1ps
module generate_code(CLK,nRST,nodes,nodeCount,characters,charCount,code,codeLen);
input CLK;
input nRST;
input integer nodeCount;//Total nodes in huffman tree
input integer charCount;//Total unique characters
input [6:0] characters[0:3];
input [23:0] nodes[0:6]; // total characters
output [3:0] code[0:3]; //[2:0] max code length <= total characters
output [3:0] codeLen[0:3];
reg [3:0] code[0:3];
reg [3:0] codeLen[0:3];
reg[3:0] tc;//temprary code reg. Holds a single bit in each byte
integer len=0;//code length
reg [23:0] tNode;
function void FindRoot;
reg [23:0] aNode;//local
integer i;
begin
for (i=0; i<nodeCount;i++) begin // For all nodes
aNode= nodes[i]; // aNode is current node
if (tNode[23:16] == aNode[14:7]) begin
tc[len]= tNode[15];//15th bit of nodes is codebit
len++;
//aNode is parent of tNode. Is it root?
if(aNode[23:16]==8'b0000_0000) begin//or frequency==nodeCount or node_id = 8'b1111_1111
return;
end else begin
tNode=aNode;
FindRoot();
end
end
end
end
endfunction
always#(posedge CLK or negedge nRST)
begin
if(!nRST) begin
// init
end
else begin
// Do code generation
integer i,j,k;
for(i= 0;i < charCount;i++) begin // For all character we are going to find codeword
for(j=0; j<nodeCount; j++) begin
tNode= nodes[j];//current node
if (characters[i] == tNode[6:0]) begin
// Got the character. tNode is a leaf nodes. Lets back track to root.
break;
end
end
len=0;
FindRoot();
for(k=0;k<len;k++) begin
if (tc[k] == 1'b0) begin
code[i][k]= 1'b0;
end else begin
code[i][k]= 1'b1;
end
end
//code[i]=2;
codeLen[i]= len;
end
end
end
endmodule
When I am assigning values to code[][], it is expected that following loop is executed. Though not all the bits of code[][] will be set. During debugging, when I come to assignment, I found that value is not being assigned (code[i][k] =1 or 0). Its getting unknown logic value X.
for(k=0;k<len;k++) begin
if (tc[k] == 1'b0) begin
code[i][k]= 1'b0;
end else begin
code[i][k]= 1'b1;
end
end
Testbench:
`timescale 1ns / 1ps
module generate_code_test;
// Inputs
reg CLK;
reg nRST;
integer nodeCount=7;//Total nodes in huffman tree
integer charCount=4;//Total unique characters
reg [6:0] characters[0:3];
reg [23:0] nodes[0:6]; // total characters
// Outputs
wire [3:0] code[0:3]; //[2:0] max code length <= total characters
wire [3:0] codeLen[0:3];
generate_code uut (
.CLK(CLK),
.nRST(nRST),
.nodes(nodes),
.nodeCount(nodeCount),
.characters(characters),
.charCount(charCount),
.code(code),
.codeLen(codeLen)
);
initial begin
// Initialize Inputs
CLK = 0;
nRST = 0;
nodeCount= 7;
charCount= 4;
characters[0]= 7'b110_0001;
characters[1]= 7'b110_0010;
characters[2]= 7'b110_0011;
characters[3]= 7'b110_0100;
nodes[0] = 24'b0000_0011_0_0000_0001_110_0001;
nodes[1] = 24'b0000_0011_1_0000_0010_110_0011;
nodes[2] = 24'b0000_0101_1_0000_0011_111_1111;
nodes[3] = 24'b0000_0101_0_0000_0100_110_0010;
nodes[4] = 24'b1111_1111_1_0000_0101_111_1111;
nodes[5] = 24'b1111_1111_0_0000_0110_110_0100;
nodes[6] = 24'b0000_0000_0_1111_1111_111_1111;
// Wait 10 ns for global reset to finish
#10;
nRST = 1;
end
parameter DELAY = 1;
always
#DELAY CLK = ~CLK;
endmodule
The code has been compiled in ModelSim 2016
I just started learning verilog. So I would really appreciate your help to show my mistakes.
Regards.
I got a fix for my problem. Not all the bits of code[][] has been set. This leads to unknown logic value in code[][] even after setting the bit. It gets solved after initializing all the bits of code[][] in always block.
I have written system verilog code for reading data from an image file (800*600 -
*.raw).
The file actually contains 800 * 600 * 3 bytes. But my code can only read upto almost
half the data.
After that the read data seems to be "00".
Valuable suggestions for resolving this is appreciated..
My code is as follows.
//`define EOF 32'hFFFF_FFFF
//`define EOF \n
reg [7:0]data_byte;
class input_video_IF;
int count;
integer input_file, fread_return,output_file;
function new ();
input_file = $fopen("test_800.raw","r");
if(input_file)
begin
$display("File OPENED");
end
else
begin
$display("File error");
end
output_file = $fopen("output_800.raw", "w");
endfunction:new
task image_file_read();
count = 0;
//while (!$feof(input_file))
while(count != 1440000)
begin
fread_return = $fread(data_byte,input_file);
count++;
$display("%d %h",count,data_byte);
//$fwrite(output_file,data_byte);
end
$finish;
$fclose(input_file);
endtask : image_file_read
endclass
program Image_read_test;
int input_file;
input_video_IF In_IF = new();
initial
In_IF.image_file_read();
endprogram
all,i need help.i encounter question about array data transaction.Please help me!
code is following.
packet is data class,and there is three queue,R,G,B,and in module "test",arith function 's return_data is no data. why?
question:though "into-arith" function,output tr_out is no data.
class packet # (int bit_depth =16);//packet class
bit [bit_depth-1:0] R[$];
bit [bit_depth-1:0] G[$];
bit [bit_depth-1:0] B[$];
endclass
//packet is data class
module test #(active_num=1920); //
packet in_tr [4];
initial begin
foreach(in_tr[i]) begin
in_tr[i] = new();
end
foreach(in_tr[j]) begin
for(int i=0;i<1920;i++) begin
in_tr[j].R.push_back(i);
end
end
process_in_tr;
end
task process_in_tr();
packet tr_out[4];
foreach(tr_out[i])begin
tr_out[i] = new();
end
tr_out[4] = into_arith(in_tr);
foreach(tr_out[j]) begin
foreach(tr_out[j].R[i]) begin
$display("%h",tr_out[j].R[i]);
end
end
endtask
function packet[4] into_arith(ref packet in_tr[4]);
packet tr_tmp[4];
foreach(tr_tmp[i]) begin
tr_tmp[i] = new();
end
for(int m=0;m<4;m++) begin
foreach(in_tr[m].R[i]) begin
tr_tmp[m].R.push_back(in_tr[m].R[i]);
tr_tmp[m].G.push_back(in_tr[m].G[i]);
tr_tmp[m].B.push_back(in_tr[m].B[i]);
end
end
return tr_tmp[4];
endfunction
endmodule
I couldn't event get this to compile in Questa, there are many syntax errors.
The three main problems are
The declaration of the function is an error. You must use a typedef when returning an aggregate type (in your case an unpacked array of packet#())
the assignment tr_out[4] = into_arith(in_tr); is illegal. You are trying to assign a unpacked array of 4 elements to the 5th element of an array, which doesn't even exist.
The return tr_tmp[4]; is also illegal. You are trying to return the non-existent 5th element of an array as the return value for a function that requires a 4-element array.
See all my corrections below:
class packet # (int bit_depth =16);//packet class
bit [bit_depth-1:0] R[$];
bit [bit_depth-1:0] G[$];
bit [bit_depth-1:0] B[$];
endclass
//packet is data class
module test #(active_num=1920); //
typedef packet#() packet4_t[4];
packet4_t in_tr;
initial begin
foreach(in_tr[j]) begin
in_tr[j] = new();
for(int i=0;i<1920;i++)
in_tr[j].R.push_back(i);
end
process_in_tr;
end
task process_in_tr();
packet4_t tr_out;
tr_out = into_arith(in_tr);
foreach(tr_out[j]) begin
foreach(tr_out[j].R[i]) begin
$display("%h",tr_out[j].R[i]);
end
end
endtask
function automatic packet4_t into_arith(ref packet4_t in_tr);
packet4_t tr_tmp;
foreach(tr_tmp[i]) begin
tr_tmp[i] = new();
tr_tmp[m].R = in_tr[m].R;
tr_tmp[m].G = in_tr[m].G;
tr_tmp[m].B = in_tr[m].B;
/* assigments above are the same as the foreach loop below
foreach(in_tr[m].R[i]) begin
tr_tmp[m].R.push_back(in_tr[m].R[i]);
tr_tmp[m].G.push_back(in_tr[m].G[i]);
tr_tmp[m].B.push_back(in_tr[m].B[i]);
end */
end
return tr_tmp;
endfunction
endmodule
I am just beginning to learn VHDL in modelsim, so i apologize in advance if what I'm doing seems really noob.
Basically what i am trying to create is a synthesizable VHDL code for a one-digit up/down BCD counter. The counter will count when "Enable" is '1', or else it stays the same. When input "Init" is initialized, the counter is set to 0 or 9 depending on the value of "Direction" input. (When "Direction" is '1', it is an up counter).
I'm just wondering if there are better tools to use for this to work other than using 100 if and else in a row.
Here is my code, I am writing a test bench for it right now, so I am not yet sure if this will even work. So if you happen to also spot some mistake please point it out for me.
Thanks a lot in advance, and here is my code
entity BCD_counter is
port(clk, direction, init, enable: in bit;
q_out: out integer);
end entity BCD_counter;
architecture behaviour of BCD_counter is
signal q: integer;
begin
process(clk)
begin
if(Clk'event and Clk = '1') then
if(direction = '1') then -- counting up
if(init = '1')then --initialize
q<=0; -- reset to 0
else
if(enable = '1')then -- counting
if (q<9) then
q<=q+1;
else
q<=0;
end if;
else
q<=q;
end if;
end if;
elsif(direction = '0') then --counting down
if(init = '1') then --initialize
q<=9; --reset to 9
else
if(enable = '1') then --counting
if (q>0) then
q<=q-1;
else
q<=9;
end if;
else
q<=q;
end if;
end if;
end if;
end if;
end process;
q_out <= q;
end architecture behaviour;
Slightly different style, but this is how I would write it
architecture behaviour of BCD_counter is
signal next_q : integer;
signal q : integer;
begin
pReg : process
begin -- process pReg
wait until clk'event and clk = '1';
if init = '1' then
q <= 0;
else
q <= next_q;
end if;
end process pReg;
pCount : process (direction, enable, q)
begin -- process pCount
next_q <= q;
if enable = '1' then
if direction = '1' then
next_q <= q + 1;
if q = 9 then
next_q <= 0;
end if;
else
next_q <= q - 1;
if q = 0 then
next_q <= 9;
end if;
end if;
end if;
end process pCount;
q_out <= q;
end architecture behaviour;
Points to note:
The register behaviour is in a separate process from the logic. I find this style is clean. Others have different opinions which normally come down to not liking having next_blah signals.
init is your reset signal, so it overrides everything else, and I put reset signals in the register process.
The first line of the counter process is what I want to happen by default. In this case it says have the next state of q be the current state.
I have the outer if be the check of enable. If we're not enabled we don't do anything, so why check direction first?
Inside each half of the direction condition the code structure is the same. Set-up what I want the normal case to be, and then check for the exception to the rule. For example: if we're going up, I set the next state to be q+1, but if q is 9 I override it with q <= 0.
I'm not using >, < in any comparisons. These are more expensive than =, and = is just fine.
Alternatively you could take the enable into the register process. It's slightly shorter, and possibly clearer. It also makes it obvious that you're expecting to use the enable pin of a register for this function.
pReg : process
begin -- process pReg
wait until clk'event and clk = '1';
if init = '1' then
q <= 0;
else
if enable = '1' then
q <= next_q;
end if;
end if;
end process pReg;
pCount : process (direction, q)
begin -- process pCount
if direction = '1' then
next_q <= q + 1;
if q = 9 then
next_q <= 0;
end if;
else
next_q <= q - 1;
if q = 0 then
next_q <= 9;
end if;
end if;
end process pCount;
The only thing that comes to my mind is that you could ommit the two
else
q<=q;
statements because this is implicitly done if none of the other conditions check out.
I do a lot of this - I created a function called modulo_increment which takes an input integer, and "modulus" integer and returns the wrapped around value.
so you can then do
q <= modulo_increment(q, 10);