Xilinx Verilog `define macro to replace wire/reg name - macros

We're trying to do something like following in verilog:
`define MY_SUFFIX suffix
wire prefix_`MY_SUFFIX;
assign prefix_`MY_SUFFIX = 1'b0;
However, the pre-processor doesn't seem to do the right substitution. There is a syntax error on the assign line ("syntax error near 'suffix'), but there is no syntax error if the assign ... line is commented out but the wire ... line isn't.
Going to simulate this with the assign... line commented out (to avoid syntax errors) gives the compilation error "prefix_ is an unknown type".
There's clearly something we're missing, but that behavior doesn't make sense!

Running this with various simulators at edaplayground gives mixed results:
http://www.edaplayground.com/x/A84
Fundamentally I don't believe Verilog is required to honor spaces (or lack thereof) around a macro. Where it's not working it was probably expanded as:
wire prefix_ suffix; // space in middle, syntax error

Just stumbled upon this post because I had the same problem. My solution was to create a macro that also accepts the prefix as an input.
It does not look very nice but it works:
`define MY_SUFFIX(name) ``name``suffix
wire `MY_SUFFIX(prefix_);
assign `MY_SUFFIX(prefix_) = 1'b0;
Or for better readability:
`define CONCAT(a,b) ``a``b
`define MY_SUFFIX suffix
wire `CONCAT(prefix_, `MY_SUFFIX);
assign `CONCAT(prefix_, `MY_SUFFIX) = 1'b0;

Related

When to use % or %variable% in AutoHotKey?

I have searched around quite a bit and have failed to find an answer. In AutoHotKey, I am not sure the difference when a single percent is used near the beginning of a line, and when a variable is enclosed between two percent signs. I usually use trial and error to find when I use one or the other, I am hoping someone could shed some light on what the difference is or explain what it is actually doing.
Here are some examples of this in action.
Example 1: I noticed if you have multiple variables along with text, scripts tend to go with the preceding percent. Such as:
some_val := Clipboard
loop 5
msgbox % "Index:" . A_Index . ", variable:" . some_val
Example 2: I often see this as well, and sometimes it appears it must be used. Is this true?
some_variable := "test text to send"
Send, %some_variable%
Wrapping in double percent signs is legacy AHK and basically there is no need to ever use it anymore. Only reason to wrap in double % would be being stuck behind in the old times, or maybe one could argue it also being more convenient, or something, to write in some cases, but I'm not buying it.
The legacy syntax is replaced by expression syntax.
The expression syntax is closer to how many other languages behave. AHK legacy syntax really is a mess.
All legacy commands (MsgBox for example) use the old legacy syntax on each parameter (unless otherwise specified).
If you specify a % followed up by a space at the start of the parameter, you're forcing AHK to evaluate an expression on that parameter instead of reading it as a legacy text parameter.
Example:
MsgBox, 5+5
We're using a legacy command, we're not starting the parameter off with a % and a space, so we're using the legacy syntax. The MsgBox is going to print the literal text 5+5 instead of 10.
MsgBox, % 5+5
Again, legacy command, but now we're forcing AHK to evaluate an expression here, 5+5.
The result of expression's evaluation is going to be passed onto the MsgBox command and the MsgBox is going to print 10.
If we wanted to MsgBox to print the literal text 5+5, and use the expression syntax to do it, we'd do MsgBox, % "5+5".
Quotation marks in expression syntax mean we're specifying a string.
Well then there's the problem of knowing when you're in expression syntax, and when you're in the legacy syntax.
By default, you're basically always in an expression.
You leave it by for example using a command or = to assign.
If the difference between a command and a function isn't clear to you, here's an example:
Command, % 7+3, % MyCoolArray[4], % SomeOtherNiceFunction(), % false
Function(7+3, MyCoolArray[4], SomeOtherNiceFunction(), false)
In the command we specified a % followed up by a space to evaluate the expressions on each parameter, and in the function, we didn't have to do that since we're already in an expression.
And if you're not clear on the difference between = and :=,
= is legacy and deprecated, it assigns plain text to a variable
:= assigns the result of an expression to a variable.
So that's what I could write from on top of my head.
If you had some more complex examples, I could try showing on them. Maybe convert some code you may have over to expression syntax, make it 100% free of legacy syntax.
And here's a good page on the documentation you should give a read:
https://www.autohotkey.com/docs/Language.htm

ARM function declaring macro

Thanks for reading first.
I'm trying to understand some code from OPTEE-OS.
This a part of macro and seems trying to declaring a function.
.macro LOCAL_FUNC name colon
.section .text.\name
.func \name
.type \name , %function
\name \colon
.endm
This function would be located in .text section.
And my question is What is the purpose of below code?
\name \colon
And also in below code,
.macro END_FUNC name
.size \name , .-\name
.endfunc
.endm
Why the .size should be written there?
Thanks for answering previously.
The \name \colon will create a label with the given name, because labels in ARM assembly language are given by a string followed by a colon. This will allow code following an expansion of the LOCAL_FUNC macro to be called by branching to a label of the same name.
The \size directive calculates the amount of space that is being used by the thing that a symbol points to, which means that the linker can then exclude that symbol entirely if it is unused. See this blog post for more on \size.

How do I know which Systemverilog macros are defined when using Modelsim or Questasim?

I'm using Questasim 10.4c to simulate a Systemverilog design that uses the `ifdef compiler directive at a bunch of places. Example:
`ifdef FOR_SIMULATION_ONLY
<code>
`endif
After compiling, I haven't found any way to get Questasim to be able to tell me explicitly whether FOR_SIMULATION_ONLY has been defined, though. I've dug through the user guide and command reference manual and the closest thing I've found is putting a -E option in all my vlog compile statements and then examining the files created to see if FOR_SIMULATION_ONLY is defined. Can Questasim tell me, though, whether it's been defined without having to use the vlog -E method?
There is no switch to do that. You can put in
`ifdef FOR_SIMULATION_ONLY
$info("FOR_SIMULATION_ONLY defined");
`endif
and get a message at elaboration time.

How to declare dynamic arrays in system verilog

I am trying to declare a dynamic array in SystemVerilog source, but getting an error like:
Dynamic range only allowed in SystemVerilog.
The tool I am using is ModelSim. The piece of code is like this:
module sv1;
reg [7:0] memory []; // 8 bit memory with 16 entries
endmodule
What are probable problems?
There is no problem with your code. The only issue is that the simulator you are using does not support SystemVerilog.
You can try your SystemVerilog code at http://edaplayground.com
Most tools treat source files on the command line or project list as Verilog unless you give the file a *.sv extension to have them recognized as SystemVerilog. The reason is there are still a number of tools that do not support SystemVerilog and you have to explicitly ask for it.
There is also a ModelSim -sv switch which treats all files as SystemVerilog, but you can run into compilation problems if your legacy Verilog code uses SystemVerilog reserved keywords like bit.

how I can define variable name with " write " command in fortran

I need to define a variable name for different files inside a Fortran code, while I 'm using this commands
open(unit=5,file="plot.sm")
write(unit=zbin_str,fmt='(f5.2)') zbin
plotname="LF_z"//zbin_str//".ps"
write(5,"dev postencap" plotname)
write(5,"toplabel LF for",//zbin_str//)
I'm receiving these errors :
Syntax error, found '//' when expecting one of: ( * <IDENTIFIER> <CHAR_CON_KIND_PARAM> <CHAR_NAM_KIND_PARAM> <CHARACTER_CONSTANT> ...
write(5,"toplabel LF for",//zbin_str//)
error #6355: This binary operation is invalid for this data type. [PLOTNAME]
write(5,"dev postencap" plotname)
An arithmetic or LOGICAL type is required in this context.
write(5,"dev postencap" plotname)
How I can define the available name inside the Fortran code??
Thanks
Neither of these lines
write(5,"dev postencap" plotname)
write(5,"toplabel LF for",//zbin_str//)
is well-formed; that's what the compiler is trying to tell you.
Beyond that, I'm not sure what you are trying to do or, therefore, how to fix it. Unless you use keywords your Fortran compiler will understand the 2nd argument in a write statement to be the format specifier in which you want to present the output. I can't see how either "dev postencap" plotname or "toplabel LF for",//zbin_str// can be made into a valid format specifier. Perhaps what you want is
write(5,'(a32)') "dev postencap"//plotname
write(5,'(a32)') "toplabel LF for"//zbin_str
Anything more would be based on guesswork. If this doesn't answer your question explain it more clearly if you can.