I'm running into a weird issue working with SystemVerilog on DVT. The code snippet in question looks something like this:
class parent;
int A;
function void foo();
A = 5;
endfunction
endclass
class childA extends parent;
function void foo();
bit test_one; //Does not flag as a syntax error.
super.foo();
bit test_two; //Flags as error: Expected endfunction, found bit.
endfunction //Subsequently: Expected endclass, found endfunction
endclass //And lastly: Unexpected token: Endclass
As far as I know it is legal to call any hidden parent function using super. but this behavior is perplexing me. Can someone tell me if this is legal SV syntax? Or if not: What's the reasoning behind this?
It is illegal syntax. All variables in a task or function must be declared before any operation. See IEEE Std 1800-2012 ยง 13 Tasks and functions (subroutines)
Legal syntax is:
function void foo();
bit test_one;
bit test_two;
super.foo();
endfunction
The only exception is a begin-end block in which case the variable can be declared at the top of the begin-end block before any operation (but you can nest begin-end block). This does however limit scope access and may be less readable. So it not a good practice
function void foo();
bit test_one;
super.foo();
begin
bit test_two; // only in scope within this begin-end
begin
bit test_three; // not the same 'test_three' as below, different scope
end
begin
bit test_three; // not the same 'test_three' as above, different scope
end
// both 'test_three's are out of scope
end
// 'test_two' both 'test_three's are out of scope
endfunction
General best practice is to always declare your variables at the top. I prefer adding empty space between variable declarations and operations a visual separator; makes reading and modifying a ascetically easier.
function void foo();
bit test_one;
bit test_two;
super.foo();
endfunction
Related
I met a problem when I trying to modify a queue of class in systemverilog function.
Here are the codes:
module my_module;
class dscr;
logic mode;
function void print_dscr;
$display("mode = %d", this.mode);
endfunction
endclass
dscr a_dscr_q[$];
dscr b_dscr_q[$];
initial begin
descriptor_decode(0, a_dscr_q);
for (int I=0; I<a_dscr_q.size(); i++)
a_dscr_q[i].print_dscr();
descriptor_decode(1, b_dscr_q);
for (int I=0; I<a_dscr_q.size(); i++)
a_dscr_q[i].print_dscr();
for (int I=0; I<b_dscr_q.size(); i++)
b_dscr_q[i].print_dscr();
end
function void descriptor_decode(logic mode, ref dscr dscr_q[$]);
dscr dscr_dec = new;
dscr_dec.mode = mode;
dscr_q.pushback(dscr_dec);
endfunction
endmodule
I am trying to create different class queue in function "descriptor_decoder", with different value of input mode. In function, I firstly create a new dscr class and then push it to a class queue. However the simulation result are:
mode = 0
mode = 1
mode = 1
The first time I call the function, it did push back the correct class into a_dscr_q. But the second function call, it seems the class is push back into both a_dscr_q and b_dscr_q. I am quite confused, What happened in here?
Your code was made illegal syntax in the IEEE 1800-2009 LRM because of the very problem you are experiencing. Most tools now report this as an error.
Your descriptor_decode is function with a static lifetime, and the dscr_dec variable declared inside it has a static lifetime as well.
You are not allowed to have an initialization on a variable whose lifetime is implicitly static and has the option to be declared automatic. This is because unlike most programming languages, the default lifetime of variables in a SystemVerilog function is static, and initialization of static variables happens once before time 0, not each occurrence of calling the function. In your example, you are expecting dscr_dec to behave as an automatic.
So you need to make one of the following code changes:
explicitly declare dscr_dec automatic
declare the function automatic, which makes variables declared inside it implicitly automatic
declare the module automatic, which makes functions declared inside it implicitly automatic
split the declaration and initialization do that the initialization happens when the function gets called.
I'd like to store a reference to an array/queue inside a class. It's doesn't seem possible to do this, though.
I'd like to do something like this:
class some_class;
// class member that points to the 'q' supplied as a constructor arg
??? q_ref;
function new(ref int q[$]);
this.q_ref = q;
endfunction
endclass
If q_ref is merely defined as int q_ref[$], then the assignment operator will create a copy, which isn't what I want. I'd like changes in 'q' to be visible inside the class.
Is there some hidden section in the LRM that shows how this can be done?
I'm not looking for the obvious "you have to wrap the array/queue in a class answer", but for something that allows me to interact with code that uses native arrays/queues.
There are only three variable types in SystemVerilog that can store references: class, event, and virtual interfaces variables.
You have to wrap the array/queue as a member in a class object. Then, any method of that class can be used in an event expression. Any change to a member of the class object causes a re-evaluation of that method. See the last paragraph and example in section 9.4.2 Event control of the 1800-2012 LRM.
So, the only solution for you would be to wrap the queue in a class. The latter is always assigned by a reference, as in this example:
class QueueRef #(type T = int);
T queue[$];
function void push_back(T t);
queue.push_back(t);
endfunction // push_back
endclass // Queue
class some_class;
QueueRef q_ref;
function new(QueueRef q);
this.q_ref = q;
endfunction
endclass
program test;
QueueRef q = new;
some_class c = new (q);
initial begin
q.push_back(1);
q.push_back(2);
$display(c.q_ref.queue);
end
endprogram // test
I am trying to declare a extern function in an interface and implementing it in a separate file in an effort to make our testharness generic.
What i want is something like this:
in_check.sv
interface in_check;
extern function bit fu_check(int num, logic state);
endinterface
in_impl.sv
interface in_impl(in_check uin_check);
function bit uin_check.fu_check(int num, logic state);
if(state) return num;
else return 0;
endfunction
endinterface
But Questasim gives me this error message:
** Error: (vsim-3787) in_impl.sv: Exported function 'uin_check.fu_check' arguments don't match those of export/extern task in interface 'in_check'.
This indicated that it should at least be possible with implicit declaration, but implicitly defined functions (i.e. extern function fu_check) gives this error message:
** Error: (vlog-13069) in_check.sv(20): near "fu_check": syntax error, unexpected IDENTIFIER.
Tasks work perfectly, and I can live with having to use an output argument. However, I would much prefer to be able to give a return value.
How can I make this work?
Bonus question: The LRM seems a bit light in info on this, is the implementation tool specific?
Blazing ahead with newfound knowledge of SystemVerilog's inner workings I've set out to use one of these fandangled pass-by-reference features to update a classes' counter in the constructor of another class. The setup (stripped to the basics) looks somewhat like this:
class my_queue;
int unsigned num_items; //Want to track the number of items this Queue has seen.
function push_new_item();
item new_item = new(num_items);
endfunction
endclass
class parent_item;
int unsigned x_th_item;
function new(ref int unsigned num_items);
x_th_item = num_items;
num_items += 1; //This should increase the counter in num_items.
endfunction
endclass
class item extends parent_item;
function new(ref int unsigned num_items);
super.new(num_items);
endfunction
endclass
The issue is that my compiler is complaining about an
Illegal connection to the ref port 'num_items' of function/task parent_item::new, formal argument should have same type as actual argument.
I have an idea on how to fix this: Moving the increment after the call to new() in push_new_items.
But then I still won't know how to correctly use pass-by-refrence in SV so what's causing the error?
Is it the other pass-by-reference or maybe a syntactical error?
You do not need ref semantics for this, use an inout argument.
inout's are copied-in upon entry and copied-out upon return of a task or function. The type compatibility requirements are much stricter as you have seen for ref arguments.
The only occasion you must use a ref argument isin time consuming tasks and you need to see active updates to the arguments before the task returns.
task my_task(ref bit tclock);
#(posedge tclock) // this would hang if tclock was an input
endtask
Another place you might want to use a ref argument is as an optimization when the argument type is a large object like an array. But passing a single int by reference is actually slower than copying its value directly.
Qiu did point me to the issue with my code. My problem was that, whilst the variables were declared correctly on both ends, one of my constructors was written:
function new(ref int num_items);
where it should have rather been
function new(ref int unsigned num_items);
Thank you Qiu.
I'm investigating the Linux kernel where I came across multiple functions that have the following syntax. I'm confused about what this syntax means. I'm not interested what the function does, but what the syntax means.
static int __init customize_machine(void)
{
...
return 0;
}
Here, __init is a macro. It says return 0, so it returns an int, but what is the __init macro doing there?
Also, the macros are found at the end of the function name declaration:
static noinline void __init_refok rest_init(void) __releases(kernel_lock)
{
...
}
Same question: what is the purpose of this macro?
This function is a part of a linux kernel module. The __init macro can be found in linux/module.h. Use it like module_init(customize_machine) and becomes the init function of the module. Returning 0 means the module is loaded successfully.