Best way to check if variable is part of collection of enums? - system-verilog

Question

I'm currently trying to port some Specman code that takes certain actions based on whether a variable is part of an enumeration. In Specman the code looks something like this:
define COMP_STATES do_add, do_sub;
define WAIT_STATES wait_X, wait_Y;
defube RUN_STATES run_X, run_Y;
type my_states : [
do_add = 3'b000;
do_sub = 3'b001;
wait_X = 3'b010;
wait_Y = 3'b011;
run_X = 3'b100;
run_Y = 3'b101;
] (bits:3);
and then later:
if(state in [COMP_STATES, RUN_STATES]){
/* DO STUFF */
} else if(state in [WAIT_STATES]){
/* DO STUFF */
}
I now would like to do this in SystemVerilog but have hit a little bit of a snag. My currently best approach uses arrays:
my_state which_state[$] = {`COMP_STATES, `RUN_STATES};
int indexes[$] = which_state.get_index( index ) where ( index == state );
int num_indexes = indexes.size(); //If state doesn't exist in my_state then the returned array of indexes will be empty.
if(num_indexes > 0) begin /* DO STUFF */ end
But there has to be a more elegant and concise way? find_first_index comes to mind but I couldn't find what it would return in case no match was found.

Answer 1

There are a couple of ways you could do this. If you can depend on the encoding, then you can define your collection with a wildcard and use the wildcard equality operator or inside operator
let COMP_STATES = 3'b00?; // or parameter COMP_STATES = 3'b00?;
let RUN_STATES = 3'b01?; // or parameter RUN_STATES = 3'b01?;
let WAIT_STATES = 3'b10?; // or parameter WAIT_STATES = 3'b10?;
if (my_states inside {COMP_STATES,RUN_STATES})
...
else if (my_state ==? WAIT_STATES)
...
or you could just create an expression
module top;
enum bit [2:0] {
do_add = 3'b000,
do_sub = 3'b001,
wait_X = 3'b010,
wait_Y = 3'b011,
run_X = 3'b100,
run_Y = 3'b101
} my_states;
let COMP_STATES = my_states inside {do_add, do_sub};
let WAIT_STATES = my_states inside {wait_X, wait_Y};
let RUN_STATES = my_states inside {run_X, run_Y};
initial repeat(20) begin
std::randomize(my_states);
$write (my_states.name());
case(1)
COMP_STATES, RUN_STATES:
$display("=comp,run");
WAIT_STATES:
$display("-wait");
endcase
end
endmodule
Finally, if you were starting from scratch, I would suggest looking at tagged unions and their corresponding pattern matching conditional statements