What is advantage of structure? - system-verilog

Question

I'm Verilog user, so I am unfamiliar with SystemVerilog.
Now I'm trying to study structure literals.
What is advantage of using structure?

Answer 1

Structure in SystemVerilog is more or less similar to structure usage in C-language, structure is a collection of different data types, variables or constants under single name. For more details you can always refer SystemVerilog LRM IEEE Std 1800-2012 ♦ 7.2 Structures
I will here explain the more common usage and advantage of structures.
The declaration of structure can be done by variable or nets, A structure as a whole can be declared as variable by using var keyword and a structure can be defined as net using Verilog data type wire or tri, when defined as net type all members of structure should be 4-state types.
structure variable:
var struct {
logic [15:0] a, b;
logic [ 7:0] data;
logic [31:0] width;
} data_word_var;
structure net:
wire struct {
logic [15:0] a, b;
logic [ 7:0] data;
logic [31:0] width;
} data_word_net;
If we don't mentioned the type of structure by default it will be net type and note that a net type variable cannot be declared inside a structure despite a whole structure can be of net type.
Structure can be initialized as a whole
data_word_net dw = ’{16'hf0f0, 16'h1010, 8’d3, 0};
or individual members can be initialized
data_word_net dw;
dw.data = 8'b1011_1111;
It is also possibe that we can initialize using member names
data_word_net dw = ’{a:16'hf0f0, b:16'h1010, data:8’d3, width:0}; // legal
data_word_net dw = ’{a:16'hf0f0, data:8’d3, b:16'h1010, width:0}; // legal
data_word_net dw = ’{a:16'hf0f0, 8’d3, 16'h1010, width:0}; // illegal(all members should be mentioned do not mix both)
Also members can be initialized to their default values by using default keyword
typedef struct {
real r0, r1;
int i0, i1;
logic [ 7:0] a;
logic [23:0] addr;
} data_word;
data_word dw;
dw = ’{ real:1.0, default:0, r1:3.1415 };
Structure can be used through module ports
package my_pkg;
typedef struct {
logic [31:0] a, b;
} input_ports;
typedef struct {
logic [63:0] y;
} output_ports;
endpackage
module alu
(input my_pkg::input_ports inp,
output my_pkg::output_ports outp,
input wire clock);
...
endmodule
Structure can also be used as arguments to tasks and functions
module dut (...);
...
typedef struct {
logic [31:0] a, b;
logic [63:0] width;
logic [15:0] addr;
} i_pins;
function alu (input i_pins connect);
...
endfunction
endmodule
In addition to the above advantages language also supports array of structures in packed and unpacked format as shown below
typedef struct packed { // packed structure
logic [7:0] a;
logic [7:0] b;
} packet_t;
packet_t [15:0] packet_array; // packed array of 16 structures
typedef struct { // unpacked structure
int a;
real b;
} data_t;
data_t data_array [15:0]; // unpacked array of 16 structures