I have the following code, file c.sv:
virtual class C#(parameter W = 32); // line #2 where error message points
static function logic [W-1 : 0] f(input logic [W-1 : 0] in);
return ~in;
endfunction
endclass
I then call it from top.sv:
`include "c.sv"
module top(input wire [3:0] key, ouptut wire [3:0] led);
assign led = C#(4)::f(sw);
endmodule
In ModelSim 10.3d it works fine, but Quartus II x64 15.0.1 build 150 reports this error after Analysis & Synthesis:
Error (10170): Verilog HDL syntax error at c.sv(2) near text "virtual"; expecting a description
If I comment out inlcude "c.sv" and replace function call with a simple ~led then it works in the dev board.
What am I doing wrong?
Sadly, there is no way currently to support parameterised functions in Altera Quartus. You have the following courses of action available:
Raise a support ticket with Altera
Use a third-party synthesis tool and feed the netlist into Quartus
Re-factor your code to be less generic
Option 2 will of course involve forking out a non-trivial sum of money. Synopsys Design Compiler supports this construct, your mileage may vary with other tools.
For option 3 you could resort to macros, generated code or optional file compilation to achieve a similar result.
It's somewhat depressing that this capability isn't available to Altera FPGA users. For the benefit of the community please raise a ticket regardless of the course of action you choose. The more demand there is, the more likely Altera are to implement this feature.
There is some more discussion and prototyping of possible work-arounds that don't involve classes on the "Width independent functions" question.
Related
I wonder if the modules have any visibility into the hierarchy of the ports? Can the port hierarchy be printed out?
For a minimum working example, assume I have this:
module top ();
logic my_sig;
child ichild (.sig(my_sig));
endmodule : top
module child (input logic sig);
initial $display(/* SystemVerilog-Fu here */)
endmodule : child
I expect the $display to print top.my_sig -- or something that conveys my_sig name instead of just reading out the value. I looked into the DPI guide as well, but it doesn't seem to have any such facility.
Thanks in advance!
The DPI is for behavioral modeling interoperability between SystemVerilog and C. The VPI gives you the introspection you are looking for in from C. Also, many tools have a command line interface (find signals -ports in Modelsim/Questa without having to learn a complicated C API.
Explaining how to do this is too deep a discussion for SO. I suggest you read my DVCon 2016 paper on SystemVerilog introspection with examples here.
Can somebody please educate me why we need DPI-C function import to do UVM specific functions like uvm_hdl_force or uvm_hdl_deposit even when force and deposit system verilog constructs exist? What extra flexibility does the C functions give with these regards?
Thanks in advance
There's no deposit functionality in SystemVerilog, only force. Although most tools give you deposit functionality, there is no standard way to deal with it. The DPI-C give you a tool independent method.
UVM REG gives you the ability to look-up registers by string name, and build paths from string hierarchies. Although there are ways of creating this functionality without resorting to the DPI/VPI, it's far easier to use the VPI.
If your DUT is VHDL, there is no standard for interoperability between standards with hierarchical references across language boundaries.
I want to automate the generation of C source MEX files to expose C functions to MATLAB. I'm hoping to find something similar to Boost.Python which uses C++ template meta-programming to wrap existing C++ code without having to modify the underlying source. Note that I'm primarily interested in exposing functions right now, not class instances. If there isn't any library out there that does this already is there a better approach to solve this problem than template meta-programming? I've tried MATLAB's loadlibrary function but think its usage isn't intuitive for most end-users that I work with.
Currently I've been writing C source MEX wrappers manually which is very time consuming and, most importantly, its difficult to maintain the wrappers. I don't have any issue with getting my MEX wrappers to work, it's just that the time required to expose the function to MATLAB via MEX is orders of magnitude more than what it takes me to expose them to Python.
This example shows the idea of what I'd like to do. I'd like to expose the TimesTwo function to MATLAB which currently requires that I write a mexFunction that checks the input/output argument counts, converts MATLAB array pointers to C data types, calls the C function TimesTwo, then assigns the results to the MATLAB output arguments.
#include "mex.h"
#include "some_template_library.hpp"
// This is the function I want to expose
double TimesTwo(double in)
{
return 2*in;
}
// This macro would expand to generate the mexFunction gateway
// It would also define the data types and perform error checking
// I realize the actual implementation would need to be more complex than this
EXPOSEFUNCTION(TimesTwo,double in, double out)
I am working on a DSP toolchain named CrossCore Embedded Studio for SHARC Processors. The IDE is well implemented apart from the assembly language support which is very poor.
I am not sure whether or not Analog Devices will give a better support to it in a near future.
I mean, there is currently no code folding, no outlines and a very minimalistic code colouring support. I would like to quickly implement something more efficient and I was looking at a way to implement a new language definition in Eclipse Luna.
What I found is xtext. So I followed the 5 and 15 minutes tutorials and read some articles about it.
I am now ready to implement my language. Because this assembly language inherits very similar aspects from c (i.e. preprocessor directives, C/C++ comments, arithmetic operations and semicolons endings), I was actively looking at a C grammar example for Xtext.
Unfortunately I did not find anything yet. Sadly, I discovered that C or C++ cannot be easily described in Xtext because of the muliple language layers such as C-preprocessor and C. I will not admit defeat yet and I think I can implement something sufficent as I only require approximate syntax colouring, some code folding and outlines support.
Where can I find helpful examples to implement such language?
Here what the SHARC assembly language looks like:
#include <foo.h>
#include "foo.h"
#ifdef BAR
.segment/dm slow;
#else
.segment/dm fast;
#endif
label:
r1 = r2; /* Another comment */
r3 = dm( _symbol + 0 );
r5 = r3 + 1; // A comment
jump(db);
nop;
r8 = pass r8;
another_label:
{ // Not currently recognized by the assembly, but useful for readabily, I would like to enable code folding here...
r2 = 3;
}
final_label.end: nop;
.endseg;
Although I do not have a long trajectory using Xtext, what I would recommend you is to search a grammar like the one you are trying to accomplish not limiting it to Xtext. As far as I know, Xtext is built on top of Antlr, which is a powerful parser generator for reading, processing, executing, or translating structured text or binary files (from its website). Now, there are several contributions to the Antlr project in terms of grammars examples, and you can find them here.
In that repository you can find the C grammar written in Antlr, that should be a good starting point towards the Xtext grammar; it does not vary too much.
A friend of mine needs to implement some statistical calculations in hardware.
She wants it to be accomplished using VHDL.
(cross my heart, I haven't written a line of code in VHDL and know nothing about its subtleties)
In particular, she needs a direct analogue of MATLAB's betainc function.
Is there a good package around for doing this?
Any hints on the implementation are also highly appreciated.
If it's not a good idea at all, please tell me about it as well.
Thanks a lot!
There isn't a core available that performs an incomplete beta function in the Xilinx toolset. I can't speak for the other toolsets available, although I would doubt that there is such a thing.
What Xilinx does offer is a set of signal processing blocks, like multipliers, adders and RAM Blocks (amongst other things, filters, FFTs), that can be used together to implement various custom signal transforms.
In order for this to be done, there needs to be a complete understanding of the inner workings of the transform to be applied.
A good first step is to implement the function "manually" in matlab as a proof of concept:
Instead of using the built-in function in matlab, your friend can try to implement the function just using fundamental operators like multipliers and adders.
The results can be compared with those produced by the built-in function for verification.
The concept can then be moved to VHDL using the building blocks that are provided.
Doing this for the incomplete beta function isn't something for the faint-hearted, but it can be done.
As far as I know there is no tool which allow interface of VHDL and matlab.
But interface of VHDL and C is fairly easy, so if you can implement your code(MATLAB's betainc function) in C then it can be done easily with FLI(foreign language interface).
If you are using modelsim below link can be helpful.
link
First of all a word of warning, if you haven't done any VHDL/FPGA work before, this is probably not the best place to start. With VHDL (and other HDL languages) you are basically describing hardware, rather than a sequential line of commands to execute on a processor (as you are with C/C++, etc.). You thus need a completely different skill- and mind-set when doing FPGA-development. Just because something can be written in VHDL, it doesn't mean that it actually can work in an FPGA chip (that it is synthesizable).
With that said, Xilinx (one of the major manufacturers of FPGA chips and development tools) does provide the System Generator package, which interfaces with Matlab and can automatically generate code for FPGA chips from this. I haven't used it myself, so I'm not at all sure if it's usable in your friend's case - but it's probably a good place to start.
The System Generator User guide (link is on the previously linked page) also provides a short introduction to FPGA chips in general, and in the context of using it with Matlab.
You COULD write it yourself. However, the incomplete beta function is an integral. For many values of the parameters (as long as both are greater than 1) it is fairly well behaved. However, when either parameter is less than 1, a singularity arises at an endpoint, making the problem a bit nasty. The point is, don't write it yourself unless you have a solid background in numerical analysis.
Anyway, there are surely many versions in C available. Netlib must have something, or look in Numerical Recipes. Or compile it from MATLAB. Then link it in as nav_jan suggests.
As an alternative to VHDL, you could use MyHDL to write and test your beta function - that can produce synthesisable (ie. can go into an FPGA chip) VHDL (or Verilog as you wish) out of the back end.
MyHDL is an extra set of modules on top of Python which allow hardware to be modelled, verified and generated. Python will be a much more familiar environment to write validation code in than VHDL (which is missing many of the abstract data types you might take for granted in a programming language).
The code under test will still have to be written with a "hardware mindset", but that is usually a smaller piece of code than the test environment, so in some ways less hassle than figuring out how to work around the verification limitations of VHDL.