library(tibble)
library(tidyr)
pos_tweets = rbind(c(‘મને આ કાર ગમે છે’, ‘positive’),
Error: unexpected input in "pos_tweets = rbind(c(‘"
c(‘આ દૃશ્ય સુંદર છે’, ‘positive’),
Error: unexpected input in " c(‘"
c(‘આ સવારે મને મજા આવે છે’, ‘positive’),
Error: unexpected input in " c(‘"
c(‘સંગીત રોમાંચક છે’, ‘positive’),
Error: unexpected input in " c(‘"
c(‘રમેશ મારો પાકો દોસ્ત છે’, ‘positive’),
Error: unexpected input in " c(‘"
c(કમળા ખૂબ રૂપાળી છે’, ‘positive’),
Error: unexpected input in " c(\"
c(અમારું બિલાડું રમતિયાળ છે’, ‘positive’),
Error: unexpected input in " c(\"
c(લાડુ તો ભાવે જ ને’, ‘positive’),
Error: unexpected input in " c(\"
c(વાડી લીલી છે’, ‘positive’),
Error: unexpected input in " c(\"
c(ચોપડી રસપ્રદ છે’, ‘positive’)
Error: unexpected input in " c(\"
)
Error: unexpected ')' in ")"
Either single quote marks ' or double quote marks " must be used around the text.
Above are "strange" left quote and right quote, and fails the syntax check for allowed characters, and the text is not being recognized as a valid character string. It is the result of SMART QUOTES, given by WORD resulting in characters x93 and x94, instead of x22. See article I found 11/18/2018 at
https://support.office.com/en-us/article/change-curly-quotes-to-straight-quotes-and-vice-versa-017963a0-bc5f-486b-9c9d-0ec511a8fb8f
Change all left-quote to single or double, and then change all right-quote to the same.
Has nothing to do with text being Gujarati text.
c(‘મને આ કાર ગમે છે’, ‘positive’) fails
Copy the above and paste into Notepad, and then change font size to 18 to see the difference.
both of these work
> pos_tweets = rbind(c("મને આ કાર ગમે છે", "positive"))
> pos_tweets = rbind(c('મને આ કાર ગમે છે', 'positive'))
I'm on CentOS 7 trying to rebuild a kernel from source, only having edited the buildid value in the kernel.spec file. When I try to build, It goes on fine for a while and then fails.
From what I understand in the error log, it's failing due to errors in a file I never touched.
The build command I used was
rpmbuild -bb --without debug --without debuginfo --target=uname -m kernel.spec 2> build-err.log | tee build-out.log
The error log looks like this.
In file included from bench/futex-hash.c:17:0:
bench/futex.h: In function 'futex_wait':
bench/futex.h:36:10: error: 'SYS_futex' undeclared (first use in this function)
syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3)
^
bench/futex.h:45:9: note: in expansion of macro 'futex'
return futex(uaddr, FUTEX_WAIT, val, timeout, NULL, 0, opflags);
^
bench/futex.h:36:10: note: each undeclared identifier is reported only once for each function it appears in
syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3)
^
bench/futex.h:45:9: note: in expansion of macro 'futex'
return futex(uaddr, FUTEX_WAIT, val, timeout, NULL, 0, opflags);
^
bench/futex.h: In function 'futex_wake':
bench/futex.h:36:10: error: 'SYS_futex' undeclared (first use in this function)
syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3)
^
bench/futex.h:55:9: note: in expansion of macro 'futex'
return futex(uaddr, FUTEX_WAKE, nr_wake, NULL, NULL, 0, opflags);
^
bench/futex.h: In function 'futex_lock_pi':
bench/futex.h:36:10: error: 'SYS_futex' undeclared (first use in this function)
syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3)
^
bench/futex.h:66:9: note: in expansion of macro 'futex'
return futex(uaddr, FUTEX_LOCK_PI, detect, timeout, NULL, 0, opflags);
^
bench/futex.h: In function 'futex_unlock_pi':
bench/futex.h:36:10: error: 'SYS_futex' undeclared (first use in this function)
syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3)
^
bench/futex.h:75:9: note: in expansion of macro 'futex'
return futex(uaddr, FUTEX_UNLOCK_PI, 0, NULL, NULL, 0, opflags);
^
bench/futex.h: In function 'futex_cmp_requeue':
bench/futex.h:36:10: error: 'SYS_futex' undeclared (first use in this function)
syscall(SYS_futex, uaddr, op | opflags, val, timeout, uaddr2, val3)
^
bench/futex.h:87:9: note: in expansion of macro 'futex'
return futex(uaddr, FUTEX_CMP_REQUEUE, nr_wake, nr_requeue, uaddr2,
^
bench/futex.h: In function 'futex_wait':
bench/futex.h:46:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^
mv: cannot stat 'bench/.futex-hash.o.tmp': No such file or directory
make[3]: *** [bench/futex-hash.o] Error 1
make[2]: *** [bench] Error 2
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [perf-in.o] Error 2
make: *** [all] Error 2
error: Bad exit status from /var/tmp/rpm-tmp.GPuhpL (%build)
Bad exit status from /var/tmp/rpm-tmp.GPuhpL (%build)
When using the following SystemVerilog macro with INCISIV 13.10 (from http://www.edaplayground.com/x/2YG ) (line endings are \r\n)
`define CHECK_PORT_CONNECTION(PORT) \
begin \
uvm_port_list list; \
PORT.get_provided_to(list); \
if (!list.size()) begin \
`uvm_fatal("AP_CONNECT", \
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
end \
end
I get a bunch of errors (below). The only way I can get it to work is to get rid of all the \ and put the macro on 1 line. Why isn't this multi-line macro working with INCISIV? I tried it with 3 other simulators and it worked fine.
Invocation and errors:
[2014-11-17 13:53:06 EST] /bin/bash -c irun -access +rw -Q -unbuffered -uvmhome $UVM_HOME $UVM_HOME/src/uvm_macros.svh design.sv testbench.sv
irun: 13.10-p001: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
begin \
|
ncvlog: *E,NULLEI (my_defines.sv,3|9): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 3, file: testbench.sv line 7)
begin \
|
ncvlog: *E,NOIPRT (my_defines.sv,3|9): Unrecognized declaration '\ ' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
begin \
|
ncvlog: *E,NCUITEM (my_defines.sv,3|9): Not a valid compilation unit/global item: 'interface_declaration' [SystemVerilog].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
begin \
|
ncvlog: *E,NGITEM (my_defines.sv,3|9): Not a valid generate item: 'interface_declaration' [12.1.3(IEEE 2001)].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,EXPSMC (my_defines.sv,4|21): expecting a semicolon (';') [SystemVerilog].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NULLEI (my_defines.sv,4|25): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 4, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NOIPRT (my_defines.sv,4|25): Unrecognized declaration '\ ' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NCUITEM (my_defines.sv,4|25): Not a valid compilation unit/global item: 'interface_declaration' [SystemVerilog].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
uvm_port_list list; \
|
ncvlog: *E,NGITEM (my_defines.sv,4|25): Not a valid generate item: 'interface_declaration' [12.1.3(IEEE 2001)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,ILLHIN (my_defines.sv,5|8): illegal location for a hierarchical name (PORT).
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,EXPSMC (my_defines.sv,5|24): expecting a semicolon (';') [12.3.2(IEEE)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,EXPSMC (my_defines.sv,5|29): expecting a semicolon (';') [12.3.2(IEEE)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
PORT.get_provided_to(list); \
|
ncvlog: *E,NULLEI (my_defines.sv,5|33): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 5, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,NCUITEM (my_defines.sv,6|5): Not a valid compilation unit/global item: 'module/udp instance' [SystemVerilog].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,EXPLPA (my_defines.sv,6|5): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,EXPSMC (my_defines.sv,6|26): expecting a semicolon (';') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
if (!list.size()) begin \
|
ncvlog: *E,NULLEI (my_defines.sv,6|29): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 6, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPSMC (my_defines.sv,8|74): expecting a semicolon (';') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,NULLEI (my_defines.sv,8|74): zero length escaped identifier [2.7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPRPA (my_defines.sv,8|74): expecting a right parenthesis (')') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: "my_defines.sv", `define macro: uvm_file [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 45], `define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,EXPLPA (my_defines.sv,8|74): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`define macro: uvm_line [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 51], `define macro: uvm_fatal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_message_defines.svh line 156], `include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *W,UEXPSC (my_defines.sv,8|75): Ignored unexpected semicolon following SystemVerilog description keyword (end).
(`include file: my_defines.sv line 8, file: testbench.sv line 7)
$sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
|
ncvlog: *E,NULLEI (my_defines.sv,8|78): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 8, file: testbench.sv line 7)
end \
|
ncvlog: *E,NCUITEM (my_defines.sv,9|6): Not a valid compilation unit/global item: 'module/udp instance' [SystemVerilog].
(`include file: my_defines.sv line 9, file: testbench.sv line 7)
end \
|
ncvlog: *E,EXPLPA (my_defines.sv,9|6): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 9, file: testbench.sv line 7)
end \
|
ncvlog: *E,NULLEI (my_defines.sv,9|9): zero length escaped identifier [2.7.1(IEEE)].
(`include file: my_defines.sv line 9, file: testbench.sv line 7)
end
|
ncvlog: *E,EXPLPA (my_defines.sv,10|4): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
(`include file: my_defines.sv line 10, file: testbench.sv line 7)
`uvm_analysis_imp_decl(_good_xp)
|
ncvlog: *E,SVNOTY (testbench.sv,10|31): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 10)
`uvm_analysis_imp_decl(_good_xp)
|
ncvlog: *E,CLSSPX (testbench.sv,10|31): 'super' can only be used within a class scope that derives from a base class.
(`define macro: UVM_IMP_COMMON [/home/vlyubosl/playground_lib/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh line 205], `define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 10)
`uvm_analysis_imp_decl(_bad_xp)
|
ncvlog: *E,SVNOTY (testbench.sv,11|30): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 11)
`uvm_analysis_imp_decl(_bad_xp)
|
ncvlog: *E,CLSSPX (testbench.sv,11|30): 'super' can only be used within a class scope that derives from a base class.
(`define macro: UVM_IMP_COMMON [/home/vlyubosl/playground_lib/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh line 205], `define macro: uvm_analysis_imp_decl [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_tlm_defines.svh line 491], file: testbench.sv line 11)
class my_scoreboard extends uvm_scoreboard;
|
ncvlog: *E,SVNOTY (testbench.sv,14|41): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
uvm_analysis_imp_good_xp#(int, my_scoreboard) good_xp;
|
ncvlog: *E,EXPENC (testbench.sv,17|25): Expecting the keyword 'endclass'.
function void end_of_elaboration_phase(uvm_phase phase);
|
ncvlog: *E,SVNOTY (testbench.sv,23|49): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVNOTY (testbench.sv,30|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVEXTK (testbench.sv,30|36): expecting a ';' (to terminate a type_declaration).
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVEXTK (testbench.sv,30|36): expecting a ';' (to terminate a type_declaration).
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,BADQAL (testbench.sv,30|36): Lifetime or qualifier(s) 'static' not allowed before function declaration.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVNOTY (testbench.sv,30|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,EXPSMC (testbench.sv,30|36): expecting a semicolon (';') [10.3.1(IEEE)].
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,BADQAL (testbench.sv,30|36): Lifetime or qualifier(s) 'virtual' not allowed before function declaration.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,SVNOTY (testbench.sv,30|36): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,EXPSMC (testbench.sv,30|36): expecting a semicolon (';') [10.3.1(IEEE)].
(`define macro: m_uvm_component_registry_internal [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 467], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
`uvm_component_utils(my_scoreboard)
|
ncvlog: *E,BADQAL (testbench.sv,30|36): Lifetime or qualifier(s) 'virtual' not allowed before function declaration.
(`define macro: m_uvm_get_type_name_func [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 427], `define macro: uvm_component_utils [/home/vlyubosl/playground_lib/uvm-1.1d/src/macros/uvm_object_defines.svh line 330], file: testbench.sv line 30)
function new (string name, uvm_component parent);
|
ncvlog: *E,NEWOIC (testbench.sv,32|13): The class constructor method 'new' is only allowed within a class declaration.
function new (string name, uvm_component parent);
|
ncvlog: *E,EXPRPA (testbench.sv,32|41): expecting a right parenthesis (')') [A.2.6(IEEE)].
function new (string name, uvm_component parent);
|
ncvlog: *E,NOIPRT (testbench.sv,32|41): Unrecognized declaration 'uvm_component' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
function new (string name, uvm_component parent);
|
ncvlog: *E,NOTINF (testbench.sv,32|41): Interfaces are not allowed within tasks [SystemVerilog].
function new (string name, uvm_component parent);
|
ncvlog: *E,ILLPDL (testbench.sv,32|48): Mixing of ansi & non-ansi style port declaration is not legal.
function new (string name, uvm_component parent);
|
ncvlog: *E,EXPSMC (testbench.sv,32|49): expecting a semicolon (';') [12.3.2(IEEE)].
super.new(name, parent);
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ncvlog: *E,EXPRPA (testbench.sv,33|8): expecting a right parenthesis (')') [A.2.6(IEEE)].
super.new(name, parent);
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ncvlog: *E,CLSSPX (testbench.sv,33|8): 'super' can only be used within a class scope that derives from a base class.
endclass
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ncvlog: *E,MPANDC (testbench.sv,41|7): expecting the keyword 'module', 'macromodule', 'primitive', 'connectmodule','connect', 'discipline' or 'nature' [A.1].
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
The problem should be there is a white-space after the \ in the line before begin.
Notices it says "Unrecognized declaration '\ '", not "Unrecognized declaration '\'"
With the provided code on EDA-playground, I could not reproduce error. I believe that auto-format is deleting the trailing white-spaces. When I manually insert a space after the \ the errors match my exactly; and other simulators give equivalent errors.