As I know, nowadays the 'reg' type in systemverilog can used in assign statement.
In old fashion, the assign statement does use the only the 'net' type.
So I want to know that what kind of the signals are should have to be the 'net' type in systemverilog?
Update1
From here, http://www.testbench.in/IF_01_INTERFACE.html
I can find a interface declaration.
interface intf #(parameter BW = 8)(input clk);
logic read, enable;
logic [BW -1 :0] addr,data;
endinterface :intf
At this here, I want to know that why the read and enable and addr and data signal are clared logic data type? Is there any reason? Why not used reg or wire?
A net is used when there are multiple drivers on a signal, usually in conjunction with a bi-directional port, and for designs at the switch level that require strength to operate. See http://go.mentor.com/wire-vs-reg for more details.
Regarding the usage of net Dave's answer pretty much covers it.
From the IEEE Std 1800-2012,
The keyword reg does not always accurately describe user intent, as it
could be perceived to imply a hardware register. The keyword logic is
a more descriptive term. logic and reg denote the same type.
More info on the usage of logic can be found in below links.
1) Morgans answer
2) Greg's answer
Related
I'm trying to learn by myself SystemVerilog (I'm a university student and in my projects I've always used VHDL) and I have a question concerning data types. So far, I think I understood the differences, pro and cons between reg, wire and logic but I'm wondering, in this code snippet:
module example(
input clk,
input nrst,
input nset,
input up,
input [3:0] preload,
output [3:0] counter
);
what's the default type assigned to inputs and outputs? Is it logic (as it is the best choice for "everyday" circuitry)?
In SystemVerilog, wire and reg/logic are closely related, but independent concepts. logic is a datatype, and wire denotes a net (or network) signal kind. There are two basic signal kinds: nets(wire) and variables(var) In a port list declaration, the default is wire logic, meaning a 1-bit 4-state net.
The defaults start to get more involved when you specify a datatype without a kind and the other way around. For inputs, the default unspecified kind is always a net, but for outputs, as soon as you specify a datatype, the default kind becomes var. Verilog appeals to lazy engineers who do not like coding. I suggest being explicit and never reyling on defaults.
I have some examples of this posted here.
SystemVerilog interfaces have really simplified my FPGA designs. They allow me to route many signals to multiple blocks in logical groupings. I really like them. I use them with modports to indicate the in/out directions. In the two books I've read on SystemVerilog, interfaces are introduced and the syntax is shown before modports. At the end of the chapter/section, modports are introduced as a helpful way to use interfaces. As far as I can tell, I would never use an interface if the concept of a modport did not exist. So, this brings me to my question...
Are there usage cases for interfaces that make sense without using modports?
The usage case could be in implementation/synthesis or in verification/simulation. I'm mostly curious to learn something new here about interfaces. I looked for related questions but didn't see any.
modports are intended for tools (like synthesis) that compile a design with boundaries that require direction information. If you flatten out the hierarchy with an embedded interface, there's no need for directions. Simulation tools almost always do this, so interfaces used just for verification do not need modports.
Some people put modports in interfaces for verification as a way of restricting access to certain signals, but unfortunately, many simulation tools do not enforce the direction, especially when used with a virtual interface.
I am a bit confused as to if it is legal, from a standards stand point, to read a parameter from an interface.
Like so
interface foo_if #(parameter BAR=5)();
...
logic [BAR-1:0] data;
modport slave(input data, ...);
endinterface
module foobar(foo_if.slave s);
...
logic [s.BAR-1:0] bar;
logic [$bits(s.data)-1:0] m_data;
...
endmodule
I have a problem where a major synthesis tool vendor can not even handle this. And they explicitly tell you in the help message that it is not allowed to use $bits() with a interface member.
However a simulation tool from another vendor handles this perfectly as does another synthesis tool I have.
However in SystemVerilog for Design by S. Sutherland et al. it is stated:
Because the design hierarchy may not be yet fully resolved during
elaboration, it is illegal to assign a parameter, specparam, or
localparam constants a value that is derived from elsewhere in the
design hierarchy
However if I am not allowed to use parameters from interfaces, it really cripples the usefulness of interfaces.
The SystemVerilog 1800-2012 Standard on the other hand states:
25.10 Access to interface objects
Access to objects declared in an interface shall be available by
hierarchical name reference, regardless of whether the interface is
also accessed through a port connection or through a virtual
interface, and regardless of the existence of any declared modports in
that interface. A modport may be used to restrict access to objects
declared in an interface that are referenced through a port connection
or virtual interface by explicitly listing the accessible objects in
the modport. However, objects that are not permissible to be listed in
a modport shall remain accessible.
The issue here is not about access, but what is allowed in places that require constant expressions. The LRM is not very clear that interface port references are not considered hierarchical references. But the tool is not complaining about s.BAR, it is complaining about s.data, which is a variable, not a parameter. Normally, you can't use variables in constant expressions, but the LRM 20.6.2 says
The $bits function can be used as an elaboration time constant when
used on fixed-size data types; hence, it can be used in the
declaration of other data types, variables, or nets.
So $bits(s.data) should have been treated like a parameter expression.
BTW, you should be using the latest freely available IEEE 1800-2012 LRM.
In FreeBSD we have the constant _SIG_MAXSIG defined in _sigset.h. I am wondering where the meaning of this constant is defined. Obviously, this is something like the maximal signal value. However, I am looking for a definite standard, the common ground that all developers should look at when interpreting that value. The same holds true for the meaning of other constants -- what is the definite source defining their meaning?
This won't answer your question directly, because I'm unaware of a standard that specifies _SIG_MAXSIG (I don't think it is standardized), but much of what you're looking for is defined by the Single Unix Specification. Note: you have to register with the site in order to download the specification.
Section XSH 2.4 explains the signal-related concepts. I don't see anything about the maximum number of signals though, other than SIGRTMIN and SIGRTMAX--which are for real-time signals.
In VHDL, I often use records to group related signals into something that can be passed around as a single object, e.g. in a port map. What's the MyHDL way of doing this?
Interfaces are available in the 0.9-dev and
are straightforward. If you have an object
(class) with Signals in it it will be name
extended in conversion.
It is explained in the MEP
http://www.myhdl.org/doku.php/meps:mep-107
More examples available here (I realize it
is not well documented - yet):
https://bitbucket.org/cfelton/minnesota
Also, a small example available here:
http://www.edaplayground.com/s/130/941