How do I convert strings to enums in SystemVerilog? - system-verilog

I have command-line plusargs that I want to map to enumerated values.
vsim foo +MY_PLUSARG=BAR
How do I get the string "BAR" to become the enum BAR?

If you are using UVM 1.2 or have access to the library, you may want to use uvm_enum_wrapper class to do the conversion. It is a template class wrapper defined in uvm_globals.svh and you can use it as follows:
typedef enum {BISTRO, COFFEE_SHOP, BAR} places_e;
typedef uvm_enum_wrapper#(places_e) places_wrapper;
places_e place;
places_wrapper::from_name("BAR", place);
Quite like the code you provided in this solution, the wrapper class works by traversing the enum entries and creating an assoc array for a enum[string] map for the given enum (supplied as template parameter). So if you are using UVM 1.2, don't repeat.

The idea behind this solution is to avoid a case statement that hardcodes the members of your enumerated type. You want to be able to change the type in one play.
Let's say you have the following enum:
typedef enum {BISTRO, COFFEE_SHOP, BAR} places_e;
You want your user to be able to type:
vsim top +MEET_PLACE=BAR
Now you want to translate the string "BAR" to the enum 'Bar'.
You can do this:
typedef enum {BISTRO, COFFEE_SHOP, BAR} places_e;
module top;
places_e place_map[string];
function void make_map;
places_e pl;
pl = pl.first();
do begin
place_map[pl.name()]=pl;
pl = pl.next();
end while (pl != pl.first());
endfunction // make_map
function string get_list;
string ss;
places_e pl;
pl = pl.first();
ss = "";
do begin
ss = {ss, " ",pl.name()};
pl = pl.next();
end while (pl != pl.first());
return ss;
endfunction // get_list
initial begin
string place_str;
places_e place;
make_map;
if (!$value$plusargs("MEET_PLACE=%s", place_str)) begin
$display("You must choose a MEET_PLACE");
$finish;
end
if (! place_map.exists(place_str)) begin
$display("You must choose from this list: %s", get_list());
$finish;
end
place = place_map[place_str];
$display("Let's meet at a %s!", place.name());
end // initial begin
endmodule // top

Related

How to use let with typedef signals?

I'm trying to use let-constructs instead of `define in my TB to access some signals via hierarchical paths. It's not going that great. "Normal" signals seems to work and I can access them, but typedef-signals act strange.
Here's a super simple example code that I use to trigger the error:
module dut();
// Create a type
typedef struct {
int foo;
int bar;
} ty_fooBar;
// Instantiate the type
ty_fooBar fooBar;
// Create an "alias" for fooBar
let fooBar2 = fooBar;
// Assign some values and try to access the struct members
initial begin
fooBar.foo = 3;
fooBar.bar = 7;
$display("fooBar: %p", fooBar );
$display("fooBar2: %p", fooBar2 );
$display("fooBar.fooBar: %p", fooBar.foo );
// $display("fooBar2.fooBar: %p", fooBar2.foo ); <- ERROR
end
endmodule
Simulation gives this result:
# fooBar: '{foo:3, bar:7}
# fooBar2: '{foo:3, bar:7}
# fooBar.fooBar: 3
So, fooBar should now be the same as fooBar2, ModelSim shows this with the $display command, but for some reason I can access fooBar.foo but not fooBar2.foo. I tried reading the IEEE standard but that didn't enlighten me.
What's the deal with let and typedef? Do I have some profound misunderstanding?
The let statement combines the flexibility of a `define macro with the well formed structure of function.
Like a macro. the let arguments get replaced into the body of its definition. they may be typeless.
Like a function, a let declaration is local to a scope, including a package that can be imported. References to identifiers that are not arguments are searched from the point of the declaration. And finally the problem that you are facing is that a let statement can only be called where an expression is allowed. In fact it places parenthesis around the body before substituting.
So your reference to fooBar2.foo gets expanded as (fooBar).foo which is not legal.

Distinguishing between local data member and child-class data member in an inline constraint

I have a class with a rand data member i. This class (child) is a member of class parent, which also has a data member i. I would like to constrain the value of i in the child class to be the same as the value of i in the parent class. I want to do something like:
c.randomize with {i==this.i;};
but the this.i doesn't seem to refer to the i data member of the parent class. (Why?)
I can do this:
function void f;
int dummy = i;
c.randomize with {i==dummy;};
endfunction
or this:
function void f;
c.randomize with {i==m.blk.p.i;}; // yuck!
endfunction
but wonder if there is a better (built-in, non-hacky) way of distinguishing between the two is.
MCVE:
class child;
rand int i;
endclass
class parent;
child c = new;
int i=1;
function void f;
c.randomize with {i==this.i;};
endfunction
endclass
module m;
initial begin : blk
parent p = new;
p.f;
$display("%p", p);
end
endmodule
https://www.edaplayground.com/x/2_8P
You want {i==local::i}. See section 18.7.1 of the 1800-2017 LRM
The reason this.i does not do what you expect is the combination of these two rules:
all class methods, including the built-in randomize method, have a built-in this argument. So c.method(args) is really method(args, c) and this becomes a variable local to the method set to the value of c
Identifiers within the with clause try to bind into the scope being randomized first before searching locally at the point where calling randomize().
So i and this.i refer to the same class variable just as if you wrote
class A;
bit i;
function void method;
i = 1;
this.i = 2;
endfunction
endclass

Store reference to array/queue in SystemVerilog

I'd like to store a reference to an array/queue inside a class. It's doesn't seem possible to do this, though.
I'd like to do something like this:
class some_class;
// class member that points to the 'q' supplied as a constructor arg
??? q_ref;
function new(ref int q[$]);
this.q_ref = q;
endfunction
endclass
If q_ref is merely defined as int q_ref[$], then the assignment operator will create a copy, which isn't what I want. I'd like changes in 'q' to be visible inside the class.
Is there some hidden section in the LRM that shows how this can be done?
I'm not looking for the obvious "you have to wrap the array/queue in a class answer", but for something that allows me to interact with code that uses native arrays/queues.
There are only three variable types in SystemVerilog that can store references: class, event, and virtual interfaces variables.
You have to wrap the array/queue as a member in a class object. Then, any method of that class can be used in an event expression. Any change to a member of the class object causes a re-evaluation of that method. See the last paragraph and example in section 9.4.2 Event control of the 1800-2012 LRM.
So, the only solution for you would be to wrap the queue in a class. The latter is always assigned by a reference, as in this example:
class QueueRef #(type T = int);
T queue[$];
function void push_back(T t);
queue.push_back(t);
endfunction // push_back
endclass // Queue
class some_class;
QueueRef q_ref;
function new(QueueRef q);
this.q_ref = q;
endfunction
endclass
program test;
QueueRef q = new;
some_class c = new (q);
initial begin
q.push_back(1);
q.push_back(2);
$display(c.q_ref.queue);
end
endprogram // test

Any way to pass enum values by name as commandline args?

Is there any way to pass the value of an enum by name from the commandline? Rather what's the cleanest solution?
I tried the below,
typedef enum int unsigned { white, black, red } colour_e;
class house;
rand colour_e colour;
string n_colour = "white";
constraint c_colour {
colour.name() == n_colour;
}
endclass: house
program top;
house paradise;
initial begin
paradise = new();
void'($value$plusargs("colour=%0s", paradise.n_colour));
if (!paradise.randomize())
$display("not randomized");
else
$display("paradise.colour = %s",paradise.colour);
end
endprogram: top
I would want to pass something like this +colour=black. so that the paradise.colour is assigned black.
vcs cribbed for using enum.name() in the constraints.
below is the error.
Error-[NYI-CSTR-SYS-FTC] NYI constraint: sys function calls
T-enum_1.sv, 9 $unit, "this.colour.name" System function calls are
not yet implemented in constraints. Remove the function call or if
possible replace it with an integral state variable assigned in
pre_randomize().
while Riviera cried as below
ERROR VCP7734 "Type of 'this.colour.name()' is not allowed in a
constraint block. Only integral types are allowed in a constraint
block." "design.sv" 9 1 ERROR VCP7734 "Type of 'n_colour' is not
allowed in a constraint block. Only integral types are allowed in a
constraint block." "design.sv" 9 1 WARNING VCP7114 "STRING value
expected for format specifier %s as parameter
paradise.colour." "testbench.sv" 13 54
which brings the question to me, does everything in the contraint block has to be of integral type (just like we cannot declare a string as rand variable)?
ANyone wants to play around the code please have a look at the code at EDA playground here
Use uvm_enum_wrapper class to do the conversion from string to corresponding enum value. It is a template class wrapper defined in uvm_globals.svh (part of UVM 1.2) and you can use it as follows:
typedef enum {white, black, red} colour_e;
typedef uvm_enum_wrapper#(colour_e) colour_wrapper;
string colour_str;
void'($value$plusargs("colour=%0s", colour_str));
colour_wrapper::from_name(colour_str, paradize.n_colour);
The wrapper class uvm_enum_wrapper works by traversing the enum entries and creating an assoc array for a enum[string] map for the given enum type (supplied as template parameter). For more details take a look at the documentation.
There is another solution for the same. If you are not using UVM 1.2 version then there is like you can take string as an input argument and convert that string argument into int type. After that you can directly cast int to enum type by $cast.
Because there is no way to convert string to enum type (except UVM 1.2) so you have to add one extra step for the same.
module Test;
typedef enum {black,red,blue} color_e; //enum declaration
color_e color; //type of enum
string cmd_str; //Commandline string input
int cmd_int; //Input string is first converted into int
initial
begin
$value$plusargs("enum_c=%0s",cmd_str); //Take input argument as string it may be 0,1 or 2
cmd_int=cmd_str.atoi(); //Now convert that string argument into int type
$cast(color,cmd_int); //Casting int to enum type
$display("Value of color is --> %p",color); //Display value of enum
end
endmodule

System Verilog: enum inside interface

I have an interface:
interface my_intf();
typedef enum logic [1:0] {
VAL_0 = 2'b00,
VAL_1 = 2'b01,
VAL_2 = 2'b10,
VAL_3 = 2'b11
} T_VAL;
T_VAL val;
endinterface
My module uses this interface:
my_intf intf;
The problem is to assign the val with a value from the enum.
I can assign it as:
intf.val = 0; (and receiving warning or error)
but not as:
intf.val=VAL_0;
Nor as
intf.val = my_intf.T_VAL.VAL_0
How I overcome that problem?
I have only dealt with packages for containing enums before, and avoid interfaces. This is how I use packages. Import the package before the module definition with which you want to use it:
import my_intf_pkg::* ;
module bla(
output my_val_t intf
);
initial begin
intf = VAL_0 ;
end
endmodule
The package containing enums might look like:
package my_intf_pkg;
typedef enum logic [1:0] {
VAL_0 = 2'b00,
VAL_1 = 2'b01,
VAL_2 = 2'b10,
VAL_3 = 2'b11
} my_val_t;
endpackage : my_intf_pkg
Note that the VAL_0 etc are global and not tied to the T_VAL typedef. Therefore I often make them a bit more unique including the typedef in the name. T_VAL_0 for T_VAL typedefs etc.
Here is an example on EDAplayground.
intf.val = 0; should be an error because you are trying to assign a integral type to an enum without a cast.
intf.val = VAL_0; is an error because VAL_0 is not defined in the current scope.
You should be able to do
intf.val = intf.VAL_0;
However, the best solution in to put shared types in a package, an import the package where needed.