Variable std_logic_vector or array entry in vhdl - aes

Question

I'm currently working on AES encryption using keys of three different sizes (128,192, and 256 bit).
I was wondering if I can declare / use a std_logic_vector of a variable size? For example, can I just have one input port and I get to know wether it's 128,192, or 256 bit based on the user input?
Or else if I choose the max key length, which is 256 bit, can I assign a 128 or 192 bit key to that std_logic_vector? Or will an error message appear?

Answer 1

If the size of key changes at run-time, you will have to declare
the corresponding objects (signals, constants, variables) with the
maximum possible size. The actual key length will then be defined by another
signal or variable. The maximum size may be defined as below.
If you declare an object of type std_logic_vector with the maximum possible size, then assigning a shorter std_logic_vector will result in an error. You will have to extend the right-hand aside of the assignment to the size of the target object first, e.g. using the following resize function from the PoC Library where I'm one of the authors:
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : std_logic_vector(vec'low to high2b);
variable res_dn : std_logic_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end function;
For example, given a 128-bit std_logic_vector named source, this can be re-sized to 256 bit with:
resize(source, 256) -- returns a 256-bit std_logic_vector
The function works like the resize function on unsigned and signed from package numeric_std.
If the key size is known at compile (elaboraton) time, then you will
have two options. A usual approach is to define the key size by a
constant and passing the key size via generics to sub-components.
The following entity test has a generic SIZE specifying the key
size. The length of ports as well as other objects, can now be defined
depending on this generic.
library ieee;
use ieee.std_logic_1164.all;
entity test is
generic (
SIZE : positive := 128); -- the default value can be omitted
port (
x : in std_logic_vector(SIZE-1 downto 0);
y : out std_logic_vector(SIZE-1 downto 0));
end entity test;
architecture rtl of test is
begin -- architecture rtl
y <= not x;
end architecture rtl;
The generic can now be bound during the instantiation of this entity,
for example:
library ieee;
use ieee.std_logic_1164.all;
entity test_tb is
end entity test_tb;
architecture rtl of test_tb is
constant SIZE : positive := 192;
signal x : std_logic_vector(SIZE-1 downto 0) := (others => '0');
signal y : std_logic_vector(SIZE-1 downto 0);
begin -- architecture rtl
dut: entity work.test
generic map (
SIZE => SIZE)
port map (
x => x,
y => y);
end architecture rtl;
Of course, the length of the actuals (right side in port map) must
match the length of the formals (left side in port map). This approach
is supported by all (major) VHDL synthesis tools. If default values
for the generics are present, then test can be directly synthesized as
top-level module.
The second option, for a fixed key-size during elaboration, would be
to use unconstrained arrays (std_logic_vector) in the port
declaration of the entity. The actual size of the array can be
determined with the length atribute, and the actual range with the
range attribute, for example:
library ieee;
use ieee.std_logic_1164.all;
entity test2 is
port (
x : in std_logic_vector;
y : out std_logic_vector);
end entity test2;
architecture rtl of test2 is
signal z : std_logic_vector(x'range);
begin -- architecture rtl
z <= x;
y <= not z;
assert false report "x'length=" & integer'image(x'length) severity note;
end architecture rtl;
The range (and length) of the port signals will then be
constrained by the associated actual in the component instantiation.
library ieee;
use ieee.std_logic_1164.all;
entity test2_tb is
end entity test2_tb;
architecture rtl of test2_tb is
constant SIZE : positive := 192;
signal x : std_logic_vector(SIZE-1 downto 0) := (others => '0');
signal y : std_logic_vector(SIZE-1 downto 0);
begin -- architecture rtl
dut: entity work.test2
port map (
x => x,
y => y);
end architecture rtl;
This works in simulation. But, I'm not sure whether it is supported by
the (major) VHDL synthesis tools. Of course, for synthesis of test2
another top-level entity is required which instantiates test2 to
constraint the array ranges.