I have this conditional macro that compiles with no errors, but the logic does not seem to work. If hours is less than 2, should print "not enough" and if 2 or more than it should print something like "enough hours".
%macro methours;
%if hours lt 2 %then footnote 'does not meet requirement ';
%else
footnote ' is enough study hours ';
%mend methours;
The letter h is greater than the digit 2 so the %ELSE clause will always execute. If HOURS is a macro variable then use &hours to test its value.
You might also need another semi-colon to mark the end of the FOOTNOTE statement. The ones you have now are part of the macro code. You could add %do ... %end to make it clearer.
%if ... %then %do;
footnote ... ;
%end;
Related
I have 60 different character arrays (Book01, Book02, ..., Book60). (For example Book01 is a 1x202040 char.). I want to do a certain procedure only on Book45 until Book58.
How do I write an IF-statement or FOR-loop, so that the procedure is only performed for character arrays Book45 until Book58? For example:
Book05 % Inserted Array for test
if Book45|Book46|Book47|Book48|Book49|Book50|Book51|Book52|Book53|Book54|Book54|Book56|Book57|Book58 % If inserted array is Book45-58
% Procedure to be performed on "Inserted Array", only if Book45-58
else
% No Procedure on Book01-44 or Book59-60
end
Thanks
as mentioned in the comment, better to put all arrays into one big array. If you insist on calling a particular array you can write:
for ii=45:58
a=eval(['Book' num2str(ii)]); %
% Procedure to be performed on a
end
but everywhere I see to try and avoid eval...
I'm just putting the comment in an answer, so I can write some code. I actually lost my matlab license yesterday, so cannot test it.
for i = 1:[largest book number]
book = eval(['Book' num2str(i)]);
if i >= 45 && i <= 58
% procedure for book45 until and including book58
else
% procedure for other books
end
end
IMHO the only reason not to use eval is because it is slow (and possibly error prone), but in this case it's not an issue.
But instead of having all these separate arrays, you could put all books in a cell array and drop the eval.
edit: but now I read that you have "No Procedure on Book01-44 or Book59-60". If the else statement is empty, then the answer by dpdp is fully sufficient.
For a certain number n I have to find the next greater number than n which is prime.
I had to solve this problem in Matlab.
Below is my code:
Solution1
function k = next_prime(n)
while n<10000000000
n=n+1;
if isprime(n)==true
k=n;
break
end
end
end
In this way the problem is correctly solved, but my initial solution was:
Solution2
function k = next_prime(n)
while n<10000000000
n=n+1;
if isprime(n)==true
k=n;
end
break
end
end
The only difference between Solution1 vs Solution2 is the break statement place.
Why Solution1 is ok and Solution2 is not ok?
The break statement in MATLAB
terminates the execution of a for or while loop. Statements in the loop after the break statement do not execute.
In solution 2 you are guaranteed to break at every loop iteration, not only if it is prime. Thus it will always only run the loop once, set n to n+1 and then break without setting k (unless coincidentally n+1 was prime).
It might help you to see it if you fix your indentation:
function k = next_prime(n)
while n<10000000000
n=n+1;
if isprime(n)==true
k=n;
end
break
end
end
so the loop does 3 things, it increments n, it checks if n is prime and then it exits, always.
In solution 1, you only exit if n is prime, which is obviously what you want.
I have some code that is executed in a for loop at the moment, but I will eventually use parfor. That is why I need to save the output for each loop separately:
for Year = 2008:2016
for PartOfYear = 1:12
% some code that produces numerical values, vectors and strings
end
end
I want to save the outputs for each loop separately and in the end merge it together, so that all the outputs are vertically concatenated, starting with Year=2008, PartOfYear = 1 in the first row, then Year = 2008, PartOfYear = 2, and so on. I am stuck as how to write this code - I looked into tables, cells, the eval and the sprintf function but couldn't make it work for my case.
you can use cell (thats what i use mostly)
check out the code
a=1; %some random const
OParray=cell(1);
idx=1;colforYear=1;colforPart=2;colforA=3;
for Year = 2008:2016
for PartOfYear = 1:12
str1='monday';
a=a+1; %some random operation
outPut=strcat(str1,num2str(a));
OParray{idx,colforYear}=Year;
OParray{idx,colforPart}=PartOfYear;
OParray{idx,colforA}=outPut;
idx=idx+1;
end
end
Steer clear of eval, it makes code very difficult to debug and interpret, and either way creating dynamic variables isnt recommended in matlab as good practice. Also, always index starting from 1 going upwards because it just makes your life easier in data handling.
You're best off creating a structure and saving each output as a value in that structure that is indexed with the same value as the one in your for loop. Something like:
Years= [2008:1:2016]
for Year = 1:length(Years)
for PartofYear= 1:12
Monthly_Out{PartofYear}= %whatever code generates your output
end
Yearly_Out{year}= vertcat(Monthly_Out{:,:});
end
Total_Output= vertcat{Yearly_Out{:,:});
I am still a bit confused about how SystemVerilog's 2012 rule 4.7 is implemented.
The rule states that in a situation like this:
module test;
logic a;
integer cnt;
initial begin
cnt = 0;
#100;
a <= 0;
a <= 1;
a <= 0;
a <= 1;
a <= 0;
end
always #(posedge a)
begin
cnt <= cnt + 1;
end
endmodule
all assignments would be scheduled on the Non Blocking Assignment queue, and must then be executed in order. The last value wins.
Up to here, it's all clear.
What happens next though is not the same for all simulators.
iverilog and Modelsim (at least the Vivado 2016/3 edition) create one event on 'a', which causes cnt to increment. This seems to also match the behaviour as illustrated by Mr Cummings at SNUG 2000
VCS however filters out the intermediate values and applies only the last one, which by the way is also the way that real flip flops work.
In this case it is not a purely hypothetical discussion, the simulation results are different, and the iverilog/modelsim behaviour could cause bugs that are very difficult to catch, because the flop toggles but no value change is seen in the waveforms.
The other point is this: if iverilog/modelsim are correct, why then are they creating one event and not two?
EDIT:
Additional note.
The example above is indeed not very meaningful.
A more realistic case would be
always #(posedge clk)
begin
clk2 <= 1'b1;
if (somecondition)
clk2 <= 1'b0;
end
always #(posedge clk2, negedge rst_n)
begin
if (!rst_n)
q <= 1'b0;
else
q <= ~q;
end
this is perfectly legal and in real hardware would never glitch.
the first always is actually logically identical to
always #(posedge clk)
begin
if (somecondition)
clk2 <= 1'b0;
else
clk2 <= 1'b1;
end
However, if you simulate the first version with ModelSim, you'll see your q happily toggling away, with clk2 constant 0. This would be a debugging nightmare.
Your last question is easy to explain. It's not that simulators create only one event, they don't- it's that only the first event schedules the #(posedge) to resume the always process and the other events happen in the NBA region before the always block resumes execution in the next active event region.
I can't justify the behavior of other simulators. You are not allowed to make multiple assignments to the same flip-flop in real hardware, so you analogy in not that simple. It's possible to have an un-timed description and get multiple (#posedge's) without time passing. So filtering would prevent that coding style.
What is the consequence of not resetting a flop inside a reset aware alaways_ff block?
Example 1:
always_ff #(posedge clk, negedge rst) begin
if (~rst) begin
reg_a <='0;
reg_b <='0;
end else begin
if (condition_1) begin
reg_a <= some_signal;
end else if (condition_2) begin
reg_b <= some signal;
end
end
end
Example 2:
always_ff #(posedge clk, negedge rst) begin
if (~rst) begin
reg_a <='0;
end else begin
if (condition_1) begin
reg_a <= some_signal;
end else if (condition_2) begin
reg_b <= some signal;
end
end
end
The only difference between example 1 and 2 is, in example 2, reg_b doesn't have any reset condition. What will be the consequence of this mistake in backend/synthesis? I've front end RTL design background with little experience in sylthesis. So, I'm trying to understand why example 2 above is a bad practice.
One obvious problem is- just after reset reg_b will be X in example 2. So if reg_b is used in any control logic then it might introduce bug in design. Other than this what other problem this can create?
I do not think that it would cause any error during synthesis or PnR.
On huge designs I did encountered some ff that were not reseted. It can avoid some unnecessary constraints on the PnR tools.
As you said however, you should be careful not to introduce bugs by using it before it was written as it will be 'X' until then.