How to make an empty datatype or conditional field in SystemVerilog - system-verilog

Question

I'd like to write code in which some inputs don't exist. I'd like to create a structure which contains those params (among other things). How can I do it? I tried to use generate, define an empty struct (typedef struct {} empty_t) and 0-size array (logic foo[0]) but all my attempts failed as syntax errors.
EDIT: I'm trying to do something like (simplified):
module foo(clk, data_in, opt_data_in);
parameter USE_OPT_IN = 1;
input logic clk;
input logic data_in;
input logic opt_data_in;
typedef struct packed {
logic data_in;
// Since it's stored in on-chip RAM I'd like it
// to be as small as possible
if (USE_OPT_IN != 0)
logic opt_data_in;
} ram_entry_t;
ram_entry_t my_ram[4096];
always_ff #(posedge clk) begin
ram_entry_t new_entry;
new_entry.data_in = data_in;
if (USE_OPT_IN != 0)
new_entry.opt_data_in = opt_data_in;
my_ram[$random() % 4096] = new_entry;
end
endmodule
This of course does not compile.
EDIT2: Above is simplified example. There is over 7 optional fields and coding 128 structs seems unreasonable - compared with just using unstructured bit field.

Answer 1

There is no such thing as an optional port or empty datatype. The code inside the module that references the port has to make sense for any situation.
There are a few things you can do
You can assign a default value to an input port that will be used if left unconnected.
You can parameterize a port type to use different structures with different number of fields. Again, the code inside the module must work for any datatype. This usually means casting the input to a known type inside the module.
You can also use an variable sized array if all the input types are the same.

Answer 2

I guess the only suggestion is to use a TYPE as a parameter to the module where the latter could be a struct with or without the field. You will also need a genarate block unless you can work with interfaces or classes. Here is a skeleton way of doing it. It would probably require yet another OPT param though for generate block. Sorry, i have not try to compile it.
module foo#(parameter type TYPE = int, parameter bit OPT = 1)
(clk, data_in, opt_data_in);
input logic clk;
input logic data_in;
input logic out_data_in;
TYPE my_ram[4096];
if (OPT) begin
always_ff #(posedge clk) begin
TYPE new_entry;
new_entry.data_in <= data_in;
new_entry.opt_data_in <= opt_data_in;
my_ram[$random() % 4096] <= new_entry;
end
else begin
always_ff #(posedge clk) begin
TYPE new_entry;
new_entry.data_in <= data_in;
my_ram[$random() % 4096] <= new_entry;
end
end
endmodule
now you can instantiate you module with different classes:
typedef struct packed {
logic data_in;
logic opt_data_in;
} ram_entry_full_t;
typedef struct packed {
logic data_in;
} ram_entry_short_t;
foo#(ram_entry_full_t, 1) foo_full(..);
foo#(ram_entry_short_t, 0) foo_short(..);

Answer 3

I'll build on #Serge answer. If you want to make your RAM entry types external to the module and use them as parameters, you can do away with the USE_OPT_IN parameter altogether, as this is redundant:
typedef struct packed {
logic data_in;
logic opt_data_in;
} ram_entry_full_t;
typedef struct packed {
logic data_in;
} ram_entry_short_t;
module foo #(parameter type TYPE = int) (clk, data_in, opt_data_in);
input logic clk;
input logic data_in;
input logic out_data_in;
TYPE my_ram[4096];
if (TYPE == type(ram_entry_full_t)) begin
always_ff #(posedge clk) begin
TYPE new_entry;
new_entry.data_in <= data_in;
new_entry.opt_data_in <= opt_data_in;
my_ram[$random() % 4096] <= new_entry;
end
end
else if (TYPE == type(ram_entry_short_t)) begin
always_ff #(posedge clk) begin
TYPE new_entry;
new_entry.data_in <= data_in;
my_ram[$random() % 4096] <= new_entry;
end
end
else begin
$error("Unsuported type ...");
end
endmodule
You could replace the if/else cascade with a case to make the code slightly more readable. You could also refactor the initialization code a bit by extracting functions to avoid duplication.
You could also use TYPE as a port for your top module, instead of data_in and opt_data_in.
For option 2, you can leave your module signature as in your question and do all the magic inside:
module foo(clk, data_in, opt_data_in);
parameter bit USE_OPT_IN = 1;
input logic clk;
input logic data_in;
input logic opt_data_in;
typedef struct packed {
logic data_in;
logic opt_data_in;
} ram_entry_full_t;
typedef struct packed {
logic data_in;
} ram_entry_short_t;
if (USE_OPT_IN) begin
always_ff #(posedge clk) begin
ram_entry_full_t new_entry;
new_entry.data_in <= data_in;
new_entry.opt_data_in <= opt_data_in;
my_ram[$random() % 4096] <= new_entry;
end
end
else begin
always_ff #(posedge clk) begin
ram_entry_short_t new_entry;
new_entry.data_in <= data_in;
my_ram[$random() % 4096] <= new_entry;
end
end
endmodule
This way, it's impossible to instantiate your module with the wrong parameter and if you don't break interface compatibility if your module is already in use somewhere.