I'm trying to determine when to activate some Altivec code paths. When I examine preprocessor macros when -qaltivec is in effect I don't see a corresponding preprocessor macro (see below).
Our worry or fear is the need for -qaltivec and -DALTIVEC=1 or similar. Users almost never read the manual so it will generate endless questions and bug reports for the platform. If RTFM was going to work, it would have happened in the last 50 years or so.
Does XL/C signal Altivec when -qaltivec is in effect? If not, is there some other way we can infer it?
Thanks in advance.
Below is from GCC111, which is a Power7 machine. I'm not sure why the compiler claims Altivec is not supported.
$ xlC -qshowmacros -qaltivec -E adhoc.cpp.proto | sort | egrep -iv 'sync'
1506-1162 (W) The altivec option is not supported for the target architecture and is ignored.
"adhoc.cpp.proto", line 2.10: 1506-296 (S) #include file <iosfwd> not found.
"adhoc.cpp.proto", line 3.10: 1506-296 (S) #include file <string> not found.
#define _AIX 1
#define _AIX32 1
#define _AIX41 1
#define _AIX43 1
#define _AIX50 1
#define _AIX51 1
#define _AIX52 1
#define _AIX53 1
#define _AIX61 1
#define _AIX71 1
#define _ARCH_COM 1
#define _ARCH_PPC 1
#define _BIG_ENDIAN 1
#define _CHAR_UNSIGNED 1
#define _IBMR2 1
#define _ILP32 1
#define _LONG_LONG 1
#define _POWER 1
#define __ALIGN 1
#define __BASE_FILE__ "adhoc.cpp.proto"
#define __BIG_ENDIAN__ 1
#define __BOOL__ 1
#define __C99_BOOL 1
#define __C99_COMPLEX 1
#define __C99_COMPOUND_LITERAL 1
#define __C99_CPLUSCMT 1
#define __C99_DESIGNATED_INITIALIZER 1
#define __C99_DUP_TYPE_QUALIFIER 1
#define __C99_EMPTY_MACRO_ARGUMENTS 1
#define __C99_FLEXIBLE_ARRAY_MEMBER 1
#define __C99_HEX_FLOAT_CONST 1
#define __C99_INLINE 1
#define __C99_LLONG 1
#define __C99_MACRO_WITH_VA_ARGS 1
#define __C99_MAX_LINE_NUMBER 1
#define __C99_MIXED_DECL_AND_CODE 1
#define __C99_MIXED_STRING_CONCAT 1
#define __C99_NON_CONST_AGGR_INITIALIZER 1
#define __C99_NON_LVALUE_ARRAY_SUB 1
#define __C99_PRAGMA_OPERATOR 1
#define __C99_RESTRICT 1
#define __C99_STATIC_ARRAY_SIZE 1
#define __C99_STD_PRAGMAS 1
#define __C99_TGMATH 1
#define __C99_UCN 1
#define __C99_VAR_LEN_ARRAY 1
#define __C99__FUNC__ 1
#define __CHAR_UNSIGNED__ 1
#define __DIGRAPHS__ 1
#define __FENCE 1
#define __FUNCTION__ __FUNCTION__
#define __GCC_PROTO_OVERRIDES_KNR_DEF 1
#define __HHW_BIG_ENDIAN__ 1
#define __HHW_RS6000__ 1
#define __HOS_AIX__ 1
#define __IBMC_NORETURN 1
#define __IBMC_STATIC_ASSERT 1
#define __IBMC__ 1210
#define __IBM_ALIGNOF__ 1
#define __IBM_ATTRIBUTES 1
#define __IBM_COMPUTED_GOTO 1
#define __IBM_DOLLAR_IN_ID 1
#define __IBM_EXTENSION_KEYWORD 1
#define __IBM_GCC_ASM 1
#define __IBM_GCC__INLINE__ 1
#define __IBM_GENERALIZED_LVALUE 1
#define __IBM_INCLUDE_NEXT 1
#define __IBM_LABEL_VALUE 1
#define __IBM_LOCAL_LABEL 1
#define __IBM_MACRO_WITH_VA_ARGS 1
#define __IBM_NESTED_FUNCTION 1
#define __IBM_PP_PREDICATE 1
#define __IBM_PP_WARNING 1
#define __IBM_REGISTER_VARS 1
#define __IBM__IMAG__ 1
#define __IBM__REAL__ 1
#define __IBM__TYPEOF__ 1
#define __ILP32__ 1
#define __LONGDOUBLE64 1
#define __MATH__ 1
#define __PPC 1
#define __PPC__ 1
#define __SIZE_TYPE__ unsigned int
#define __STDC_HOSTED__ 1
#define __STDC_VERSION__ 199901L
#define __STDC__ 1
#define __STR__ 1
#define __THW_BIG_ENDIAN__ 1
#define __THW_PPC__ 1
#define __THW_RS6000__ 1
#define __TOS_AIX__ 1
#define __XLC121__ 1
#define __XLC13__ 1
#define __XLC_BUILTIN_VAARG__ 1
#define __alignof __alignof__
#define __const const
#define __const__ const
#define __powerpc 1
#define __powerpc__ 1
#define __signed signed
#define __signed__ signed
#define __typeof __typeof__
#define __unix 1
#define __unix__ 1
#define __volatile volatile
#define __volatile__ volatile
#define __xlC__ 0x0c01
#define __xlC_ver__ 0x00000000
#define __xlc__ "12.1.0.0"
The usual macro that most compilers (gcc et al) define automatically is __VEC__ (or at least this is the symbol I usually use to test for AltiVec in cross-platform code). IBM claims that __ALTIVEC__ is also defined (see "Predefined macros") for xlc when using -maltivec or -qaltivec.
Related
Context
I'm writing code that runs in uClinux on a NIOS II processor. The FPGA is a Stratix II. The FPGA design was done by someone else who is no longer at the company and I'm not a firmware designer, just a software programmer.
Problem
The FPGA loads its configuration from a flash device on power-up. I've written a app that re-programs the flash, but I need to find a way to cause it to re-load the FPGA configuration, and I need to do it from software. Currently the only way to get the FPGA to reload is to cycle the power, but that's not possible in the customer's environment.
The language I'm writing in isn't really relevant, suffice to say that I can easily write to a hardware register at a known address, for example in Tcl: nioswr32 $reg_addr $value What I'm trying to find is some sort of reset register I can use. Maybe a JTAG interface? I found reference to a JTAG_UART, but apparently that's just for providing console functionality through JTAG. Maybe there's a hardware watchdog timer I can mess with?
Note that I'm not just trying to reset the NIOS processor. I can easily do that using busybox, but that won't reload the FPGA firmware.
Below is a copy of my system.h header which I believe was generated by SOPC Builder, so you can see what resources are available.
#ifndef __SYSTEM_H_
#define __SYSTEM_H_
/*
DO NOT MODIFY THIS FILE
Changing this file will have subtle consequences
which will almost certainly lead to a nonfunctioning
system. If you do modify this file, be aware that your
changes will be overwritten and lost when this file
is generated again.
DO NOT MODIFY THIS FILE
*/
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* system configuration
*
*/
#define ALT_SYSTEM_NAME "nios_application"
#define ALT_CPU_NAME "app_CPU"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "STRATIXII"
#define ALT_STDIN "/dev/JTAG_UART"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x03000100
#define ALT_STDIN_DEV JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/JTAG_UART"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x03000100
#define ALT_STDOUT_DEV JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/JTAG_UART"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x03000100
#define ALT_STDERR_DEV JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 100000000
#define ALT_IRQ_BASE NULL
/*
* processor configuration
*
*/
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_BIG_ENDIAN 0
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_EXCEPTION_ADDR 0x20000020
#define NIOS2_RESET_ADDR 0x00260000
#define NIOS2_BREAK_ADDR 0x03000820
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0
/*
* A define for each class of peripheral
*
*/
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_PIPELINE_BRIDGE
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_UART
#define __SPI16
#define __ALTERA_AVALON_PIO
#define __I2C8
#define __PBRIDGE
#define __ALTERA_NIOS_CUSTOM_INSTR_ENDIAN_CONVERTER
#define __ALTERA_NIOS_CUSTOM_INSTR_INTERRUPT_VECTOR
/*
* JTAG_UART configuration
*
*/
#define JTAG_UART_NAME "/dev/JTAG_UART"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x03000100
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 1
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_JTAG_UART altera_avalon_jtag_uart
/*
* SDRAM configuration
*
*/
#define SDRAM_NAME "/dev/SDRAM"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x20000000
#define SDRAM_SPAN 16777216
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 0
#define SDRAM_SDRAM_DATA_WIDTH 32
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 200.0
#define SDRAM_CAS_LATENCY 2
#define SDRAM_T_RFC 70.0
#define SDRAM_T_RP 20.0
#define SDRAM_T_MRD 6
#define SDRAM_T_RCD 20.0
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 16.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_SHARED_DATA 0
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_IS_INITIALIZED 1
#define ALT_MODULE_CLASS_SDRAM altera_avalon_new_sdram_controller
/*
* FLASH_BRIDGE configuration
*
*/
#define FLASH_BRIDGE_NAME "/dev/FLASH_BRIDGE"
#define FLASH_BRIDGE_TYPE "altera_avalon_tri_state_bridge"
#define ALT_MODULE_CLASS_FLASH_BRIDGE altera_avalon_tri_state_bridge
/*
* CFI_FLASH configuration
*
*/
#define CFI_FLASH_NAME "/dev/CFI_FLASH"
#define CFI_FLASH_TYPE "altera_avalon_cfi_flash"
#define CFI_FLASH_BASE 0x00000000
#define CFI_FLASH_SPAN 16777216
#define CFI_FLASH_SETUP_VALUE 0
#define CFI_FLASH_WAIT_VALUE 0
#define CFI_FLASH_HOLD_VALUE 0
#define CFI_FLASH_TIMING_UNITS "ns"
#define CFI_FLASH_UNIT_MULTIPLIER 1
#define CFI_FLASH_SIZE 16777216
#define ALT_MODULE_CLASS_CFI_FLASH altera_avalon_cfi_flash
/*
* BRIDGE configuration
*
*/
#define BRIDGE_NAME "/dev/BRIDGE"
#define BRIDGE_TYPE "altera_avalon_pipeline_bridge"
#define BRIDGE_BASE 0x04000000
#define BRIDGE_SPAN 256
#define BRIDGE_IS_DOWNSTREAM 1
#define BRIDGE_IS_UPSTREAM 0
#define BRIDGE_IS_WAITREQUEST 0
#define BRIDGE_ENABLE_ARBITERLOCK 0
#define ALT_MODULE_CLASS_BRIDGE altera_avalon_pipeline_bridge
/*
* TIMER configuration
*
*/
#define TIMER_NAME "/dev/TIMER"
#define TIMER_TYPE "altera_avalon_timer"
#define TIMER_BASE 0x04000000
#define TIMER_SPAN 32
#define TIMER_IRQ 2
#define TIMER_ALWAYS_RUN 0
#define TIMER_FIXED_PERIOD 0
#define TIMER_SNAPSHOT 1
#define TIMER_PERIOD 10.0
#define TIMER_PERIOD_UNITS "ms"
#define TIMER_RESET_OUTPUT 0
#define TIMER_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_LOAD_VALUE 999999
#define TIMER_MULT 0.001
#define TIMER_FREQ 100000000
#define ALT_MODULE_CLASS_TIMER altera_avalon_timer
/*
* UART1 configuration
*
*/
#define UART1_NAME "/dev/UART1"
#define UART1_TYPE "altera_avalon_uart"
#define UART1_BASE 0x04000040
#define UART1_SPAN 32
#define UART1_IRQ 3
#define UART1_BAUD 115200
#define UART1_DATA_BITS 8
#define UART1_FIXED_BAUD 1
#define UART1_PARITY 'N'
#define UART1_STOP_BITS 1
#define UART1_USE_CTS_RTS 0
#define UART1_USE_EOP_REGISTER 0
#define UART1_SIM_TRUE_BAUD 0
#define UART1_SIM_CHAR_STREAM ""
#define UART1_FREQ 100000000
#define ALT_MODULE_CLASS_UART1 altera_avalon_uart
/*
* SPI_16 configuration
*
*/
#define SPI_16_NAME "/dev/SPI_16"
#define SPI_16_TYPE "spi16"
#define SPI_16_BASE 0x04000080
#define SPI_16_SPAN 16
#define ALT_MODULE_CLASS_SPI_16 spi16
/*
* PIO_IO configuration
*
*/
#define PIO_IO_NAME "/dev/PIO_IO"
#define PIO_IO_TYPE "altera_avalon_pio"
#define PIO_IO_BASE 0x040000a0
#define PIO_IO_SPAN 16
#define PIO_IO_DO_TEST_BENCH_WIRING 0
#define PIO_IO_DRIVEN_SIM_VALUE 0
#define PIO_IO_HAS_TRI 0
#define PIO_IO_HAS_OUT 1
#define PIO_IO_HAS_IN 1
#define PIO_IO_CAPTURE 0
#define PIO_IO_DATA_WIDTH 16
#define PIO_IO_EDGE_TYPE "NONE"
#define PIO_IO_IRQ_TYPE "NONE"
#define PIO_IO_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_IO_FREQ 100000000
#define ALT_MODULE_CLASS_PIO_IO altera_avalon_pio
/*
* PIO_TRI configuration
*
*/
#define PIO_TRI_NAME "/dev/PIO_TRI"
#define PIO_TRI_TYPE "altera_avalon_pio"
#define PIO_TRI_BASE 0x040000b0
#define PIO_TRI_SPAN 16
#define PIO_TRI_DO_TEST_BENCH_WIRING 0
#define PIO_TRI_DRIVEN_SIM_VALUE 0
#define PIO_TRI_HAS_TRI 1
#define PIO_TRI_HAS_OUT 0
#define PIO_TRI_HAS_IN 0
#define PIO_TRI_CAPTURE 0
#define PIO_TRI_DATA_WIDTH 16
#define PIO_TRI_EDGE_TYPE "NONE"
#define PIO_TRI_IRQ_TYPE "NONE"
#define PIO_TRI_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_TRI_FREQ 100000000
#define ALT_MODULE_CLASS_PIO_TRI altera_avalon_pio
/*
* PIO_STATUS configuration
*
*/
#define PIO_STATUS_NAME "/dev/PIO_STATUS"
#define PIO_STATUS_TYPE "altera_avalon_pio"
#define PIO_STATUS_BASE 0x040000c0
#define PIO_STATUS_SPAN 16
#define PIO_STATUS_IRQ 4
#define PIO_STATUS_DO_TEST_BENCH_WIRING 0
#define PIO_STATUS_DRIVEN_SIM_VALUE 0
#define PIO_STATUS_HAS_TRI 0
#define PIO_STATUS_HAS_OUT 0
#define PIO_STATUS_HAS_IN 1
#define PIO_STATUS_CAPTURE 1
#define PIO_STATUS_DATA_WIDTH 16
#define PIO_STATUS_EDGE_TYPE "FALLING"
#define PIO_STATUS_IRQ_TYPE "EDGE"
#define PIO_STATUS_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_STATUS_FREQ 100000000
#define ALT_MODULE_CLASS_PIO_STATUS altera_avalon_pio
/*
* I2C_8 configuration
*
*/
#define I2C_8_NAME "/dev/I2C_8"
#define I2C_8_TYPE "I2C8"
#define I2C_8_BASE 0x040000e0
#define I2C_8_SPAN 32
#define I2C_8_IRQ 5
#define ALT_MODULE_CLASS_I2C_8 I2C8
/*
* EXTBRIDGE configuration
*
*/
#define EXTBRIDGE_NAME "/dev/EXTBRIDGE"
#define EXTBRIDGE_TYPE "pbridge"
#define EXTBRIDGE_BASE 0x10000000
#define EXTBRIDGE_SPAN 67108864
#define ALT_MODULE_CLASS_EXTBRIDGE pbridge
/*
* custom instruction macros
*
*/
#define ALT_CI_CONVERTER_N 0x00000000
#define ALT_CI_CONVERTER(A) __builtin_custom_ini(ALT_CI_CONVERTER_N,(A))
#define ALT_CI_VECTOR_N 0x00000001
#define ALT_CI_VECTOR __builtin_custom_in(ALT_CI_VECTOR_N)
/*
* system library configuration
*
*/
#define ALT_MAX_FD 5
#define ALT_SYS_CLK TIMER
#define ALT_TIMESTAMP_CLK none
/*
* Devices associated with code sections.
*
*/
#define ALT_TEXT_DEVICE SDRAM
#define ALT_RODATA_DEVICE SDRAM
#define ALT_RWDATA_DEVICE SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE CFI_FLASH
#endif /* __SYSTEM_H_ */
For reconfiguration of an FPGA the Remote System Update IP core from Intel can be used. However, this means adapting the logic of your FPGA.
1 #define NUM_PHIL 4
2
3 byte chopstick[4];
4 chopstick[0] = 1;
5 chopstick[1] = 1;
6 chopstick[2] = 1;
7 chopstick[3] = 1;
8
9 proctype phil(int id) {
10 do
11 ::printf("Philosopher %d is thinking\n",id);
12 /* ... */
13 printf("Philosopher %d is eating with forks %d and %d\n",id,id,(id+1)%4);
14 /* ... */
15 od
16 }
16a
17 init {
18 int i = 0;
19 do
20 :: i >= NUM_PHIL -> break
21 :: else -> run phil(i);
22 i++
23 od
24 }
the codes above send an error "syntax error saw 'an identifier' near 'chopstick'"
how can i define and initialize array as a global variable outside the prototype P()
thanks for helping
You would initialize the chopstick array in an init body.
#define NUM_PHIL 4
byte chopstick[4]; /* NUM_PHIL */
proctype phil (int n) { /* ... */ }
init {
chopstick[0] = 1;
/* ... */
run phil (0);
/* ... */
}
In cygwin, I have two almost identical files, the other one I did minimal modification. And on the screen the first line is identical. So I use cmp utility to compare these two files byte by byte.
$cat double.c
#include <GL/gl.h>
#include <GL/glu.h>
#include <GL/glut.h>
#include <stdlib.h>
static GLfloat spin = 0.0;
void init(void)
{
glClearColor(0.0,0.0,0.0,0.0);
glShadeModel(GL_FLAT);
}
........
$cat double1.c
#include <GL/gl.h>
#include <GL/glu.h>
#include <GL/glut.h>
#include <stdlib.h>
static GLfloat spin = 0.0;
void init(void)
{
glClearColor (0.0, 0.0, 0.0, 0.0);
glShadeModel (GL_FLAT);
}
...........
$cmp double.c double1.c
It outputs these:
double.c double1.c diffrent: line 8 char 125
So
$cmp -l double.c double1.c
It output these:
125 12 40
126 173 12
127 12 173
128 40 12
144 50 40
145 60 50
146 56 60
.........
12 is "new line", 40 is ")" and 173 is "{"
the difference in a Windows editor is illustrated as following
So how this difference come from? I am confused.
double.c
https://docs.google.com/file/d/0B5qhYcc2Fk0sZmEySUNIc1RzM3M/edit?usp=sharing
double1.c
https://docs.google.com/file/d/0B5qhYcc2Fk0sRTdoV1RDNnB2QkU/edit?usp=sharing
Would someone post the results of cpp -dM < /dev/null from a Solaris 10 or above system?
I'm having trouble locating what preprocessor macros are typically defined. Solaris documentation does not discuss it in detail [1], [2], and Google is not being very helpful.
Thanks in advance.
Solaris 11.1
#define __DBL_MIN_EXP__ (-1021)
#define __FLT_MIN__ 1.17549435e-38F
#define __CHAR_BIT__ 8
#define __WCHAR_MAX__ 2147483647
#define __DBL_DENORM_MIN__ 4.9406564584124654e-324
#define __FLT_EVAL_METHOD__ 0
#define __DBL_MIN_10_EXP__ (-307)
#define __FINITE_MATH_ONLY__ 0
#define __GNUC_PATCHLEVEL__ 3
#define sparc 1
#define __SHRT_MAX__ 32767
#define __LDBL_MAX__ 1.18973149535723176508575932662800702e+4932L
#define __unix 1
#define __LDBL_MAX_EXP__ 16384
#define __SCHAR_MAX__ 127
#define __USER_LABEL_PREFIX__
#define __STDC_HOSTED__ 1
#define __LDBL_HAS_INFINITY__ 1
#define __DBL_DIG__ 15
#define __FLT_EPSILON__ 1.19209290e-7F
#define __LDBL_MIN__ 3.36210314311209350626267781732175260e-4932L
#define __unix__ 1
#define __DECIMAL_DIG__ 36
#define __LDBL_HAS_QUIET_NAN__ 1
#define __GNUC__ 3
#define __DBL_MAX__ 1.7976931348623157e+308
#define __DBL_HAS_INFINITY__ 1
#define __SVR4 1
#define __DBL_MAX_EXP__ 1024
#define __LONG_LONG_MAX__ 9223372036854775807LL
#define __sparc__ 1
#define __GXX_ABI_VERSION 1002
#define __FLT_MIN_EXP__ (-125)
#define __DBL_MIN__ 2.2250738585072014e-308
#define __DBL_HAS_QUIET_NAN__ 1
#define __sun 1
#define __REGISTER_PREFIX__
#define __NO_INLINE__ 1
#define __FLT_MANT_DIG__ 24
#define __VERSION__ "3.4.3 (csl-sol210-3_4-20050802)"
#define __sparc 1
#define sun 1
#define unix 1
#define __SIZE_TYPE__ unsigned int
#define __ELF__ 1
#define __FLT_RADIX__ 2
#define __LDBL_EPSILON__ 1.92592994438723585305597794258492732e-34L
#define __FLT_HAS_QUIET_NAN__ 1
#define __FLT_MAX_10_EXP__ 38
#define __LONG_MAX__ 2147483647L
#define __FLT_HAS_INFINITY__ 1
#define __PRAGMA_REDEFINE_EXTNAME 1
#define __LDBL_MANT_DIG__ 113
#define __WCHAR_TYPE__ long int
#define __FLT_DIG__ 6
#define __INT_MAX__ 2147483647
#define __FLT_MAX_EXP__ 128
#define __DBL_MANT_DIG__ 53
#define __WINT_TYPE__ long int
#define __LDBL_MIN_EXP__ (-16381)
#define __LDBL_MAX_10_EXP__ 4932
#define __DBL_EPSILON__ 2.2204460492503131e-16
#define __sun__ 1
#define __svr4__ 1
#define __FLT_DENORM_MIN__ 1.40129846e-45F
#define __FLT_MAX__ 3.40282347e+38F
#define __FLT_MIN_10_EXP__ (-37)
#define __GNUC_MINOR__ 4
#define __DBL_MAX_10_EXP__ 308
#define __LDBL_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966L
#define __PTRDIFF_TYPE__ int
#define __LDBL_MIN_10_EXP__ (-4931)
#define __LDBL_DIG__ 33
#jens:
Sparc systems from Solaris 10 onwards are always 64bit. X64 systems came in with Solaris 10, though you could still boot a 32bit x86 kernel.
$ isainfo
amd64 i386
$ isainfo -b
64
$ isainfo -v
64-bit amd64 applications
avx xsave pclmulqdq aes sse4.2 sse4.1 ssse3 popcnt tscp ahf cx16 sse3
sse2 sse fxsr mmx cmov amd_sysc cx8 tsc fpu efs f16c rdrand
32-bit i386 applications
avx xsave pclmulqdq aes sse4.2 sse4.1 ssse3 popcnt tscp ahf cx16 sse3
sse2 sse fxsr mmx cmov sep cx8 tsc fpu efs f16c rdrand
/usr/bin/isainfo is your friend, from the command line.
From a programmatic point of view, examine the #defines in <sys/feature_tests.h>. You'll notice _LP64 ...
So, if you have a carry out of 1 on addition with unsigned numbers, you have overflowed, and if you have a carry out of 0 with subtraction, you have underflowed. Does this work in every case, though?
If you do 5-0:
0101
-0000
=
0101
+(1111 + 1)
=
0101
+0000
= 0101... there is a carry out of zero here, instead of 1. How does one account for this case? Is there a different way to do it?
(using MIPS architecture, or anything else)
---Edit
Thanks Amadan. I understand that part, though. My problem is just that zero seems to be a special case. It does not seem to follow what normal numbers do: in my example above, there is no carry out of 1.
I'm doing circuit design working with an ALU at the moment and trying to implement the overflow detection, when this one case came up that doesn't follow what the others do.
We are assuming that with subtraction, the second operand is preinverted (twos complement) before going into the ALU (then added to the first operand). So, whenever the "invert_b" for subtraction is set to 1, b is inverted and we assume that the case we are checking for is subtraction, which should have a carry out of 1.
I believe the msbit carry out bit on its own covers unsigned and for signed you look to see if the carry in to the msbit and the carry out differ.
5-0 does not overflow because the result fits in the number of bits available. The same way that 15-1 does not overflow a 4 bit system for signed numbers
5 - 0 = 0101 + 1111 + 1
1
0101
+1111
=====
11111
0101
+1111
=====
0101
so 5 - 0 certainly carries out a 1, since this is a subtract that is not an overflow
15 - 1 = 1111 + ~1 with the carry in set
1
1111
1110
====
11111
1111
1110
====
1110
a subtract with a 1 out is not an unsigned overflow as you stated
Likewise -1 - 1 = 1111 + ~1 with the carry in bit set
11111
1111
1110
====
1110
the carry in to the last bit is a 1 the carry out is a 1 they match, no signed overflow.
8 + 8 = 1000 + 1000 with the carry in clear
0
1000
+1000
=====
10000
1000
+1000
=====
0000
unsigned overflow.
hmmm 4 + 4
0
0100
+0100
=====
01000
0100
+0100
=====
1000
unsigned add the carry out is 0 this is not an unsigned overflow. but this is a signed overflow because the carry in to the msbit and carry out differ. +4 + +4 = +8, in a 4 bit signed system you cannot represent +8, so the signed overflow is accurate.
No matter how many bits the weird numbers are all zeros and a one and the rest zeros, 0 and 8 or -8 for a 4 bit system.
Make a chart either with 2, 3, or 4 bit numbers all combinations and manually look through all of them to see that they make sense. whatever you find will scale no matter how many bits wide, a 100 bit adder works like a 10 bit adder...
add C V unsigned signed
00 + 00 = 000 0 0 0 + 0 = 0 0 + 0 = 0
00 + 01 = 001 0 0 0 + 1 = 1 0 + 1 = 1
00 + 10 = 010 0 0 0 + 2 = 2 0 + -2 = -2
00 + 11 = 011 0 0 0 + 3 = 3 0 + -1 = -1
01 + 00 = 001 0 0 1 + 0 = 1 1 + 0 = 1
01 + 01 = 010 0 1 1 + 1 = 2 1 + 1 = 2 signed cannot represent a +2
01 + 10 = 011 0 0 1 + 2 = 3 1 + -2 = -1
01 + 11 = 100 1 0 1 + 3 = 4 1 + -1 = 0 unsigned cannot represent +4
10 + 00 = 010 0 0 2 + 0 = 2 -2 + 0 = -2
10 + 01 = 011 0 0 2 + 1 = 3 -2 + 1 = -1
10 + 10 = 100 1 1 2 + 2 = 4 -2 + -2 = -4 neither +4 nor -4 will fit in 2 bits
10 + 11 = 101 1 1 2 + 3 = 5 -2 + -1 = -3 neither +4 nor -3 will fit in 2 bits
11 + 00 = 011 0 0 3 + 0 = 3 -1 + 0 = -1
11 + 01 = 100 1 0 3 + 1 = 4 -1 + 1 = -2 +4 does not fit in 2 bits
11 + 10 = 101 1 1 3 + 2 = 5 -1 + -2 = -3 neither +5 nor -3 fit in 2 bits
11 + 11 = 110 1 0 3 + 3 = 6 -1 + -1 = -2 6 does not fit in 2 bits
sub
00 - 00 = 100 0 0
00 - 01 = 011 1 0 0 - 1 = -1 -1 does not fit in an unsigned result
00 - 10 = 010 1 1 0 - 2 = -2 0 - -2 = +2
00 - 11 = 001 1 0 0 - 3 = -3
01 - 00 = 101 0 0
01 - 01 = 100 0 0
01 - 10 = 011 1 1 1 - 2 = -1 1 - -2 = 3
01 - 11 = 010 1 1 1 - 3 = -2 1 - -1 = 2
10 - 00 = 110 0 0
10 - 01 = 101 0 1 -2 - 1 = -3
10 - 10 = 100 0 0
10 - 11 = 011 1 0 2 - 3 = -1
11 - 00 = 111 0 0
11 - 01 = 110 0 0
11 - 10 = 101 0 0
11 - 11 = 100 0 0
The code that generated the above
printf("add\n");
for(ra=0;ra<4;ra++)
{
for(rb=0;rb<4;rb++)
{
rd=(ra&1)+(rb&1);
rc=ra+rb;
rd=(rd>>1)&1;
re=(rc>>2)&1;
if(re) c=1; else c=0;
if(rd!=re) v=1; else v=0;
if(ra&2) printf("1"); else printf("0");
if(ra&1) printf("1"); else printf("0");
printf(" + ");
if(rb&2) printf("1"); else printf("0");
if(rb&1) printf("1"); else printf("0");
printf(" = ");
if(rc&4) printf("1"); else printf("0");
if(rc&2) printf("1"); else printf("0");
if(rc&1) printf("1"); else printf("0");
printf(" %u %u\n",c,v);
}
}
printf("sub\n");
for(ra=0;ra<4;ra++)
{
for(rb=0;rb<4;rb++)
{
rd=(ra&1)+((~rb)&1)+1;
rc=ra+((~rb)&3)+1;
rd=(rd>>1)&1;
re=(rc>>2)&1;
if(re) c=0; else c=1;
if(rd!=re) v=1; else v=0;
if(ra&2) printf("1"); else printf("0");
if(ra&1) printf("1"); else printf("0");
printf(" - ");
if(rb&2) printf("1"); else printf("0");
if(rb&1) printf("1"); else printf("0");
printf(" = ");
if(rc&4) printf("1"); else printf("0");
if(rc&2) printf("1"); else printf("0");
if(rc&1) printf("1"); else printf("0");
printf(" %u %u\n",c,v);
}
}
Now your question was talking about unsigned numbers yes? so you may not care about the V bit nor the right half, the signed half.
Here is some HDL/RTL for a small 16 bit processor I implemented:
case 4b0000:
{
//0000 add rd,rs
op_a = bundle(1b0,reg[bundle(2b0,inst[4;8])].value);
op_b = bundle(1b0,reg[bundle(2b0,inst[4;4])].value);
op_res = op_a + op_b;
reg[1].value[CBIT] <= op_res[16];
reg[1].value[NBIT] <= op_res[15];
if(op_res[16;0] == 16h0000)
{
reg[1].value[ZBIT] <= 1b1;
}
else
{
reg[1].value[ZBIT] <= 1b0;
}
if((op_a[15] == op_b[15]) && (op_res[15] != op_b[15] ) )
{
reg[1].value[VBIT] <= 1b1;
}
else
{
reg[1].value[VBIT] <= 1b0;
}
reg[bundle(2b0,inst[4;8])].value <= op_res[16;0];
}
case 4b0001:
{
//0001 sub rd,rs
op_a = bundle(1b0,reg[bundle(2b0,inst[4;8])].value);
op_b = bundle(1b0,reg[bundle(2b0,inst[4;4])].value);
op_res = op_a - op_b;
reg[1].value[CBIT] <= (~op_res[16]);
reg[1].value[NBIT] <= op_res[15];
if(op_res[16;0] == 16h0000)
{
reg[1].value[ZBIT] <= 1b1;
}
else
{
reg[1].value[ZBIT] <= 1b0;
}
if((op_a[15] != op_b[15]) && (op_res[15] == op_b[15] ) )
{
reg[1].value[VBIT] <= 1b1;
}
else
{
reg[1].value[VBIT] <= 1b0;
}
reg[bundle(2b0,inst[4;8])].value <= op_res[16;0];
}
I have/had seen the msbit thing for signed overflow in other logic and couldnt find a case where it didnt match the carry in vs carry out method when trying every possible combination in a head to head analysis.
If I went overboard with the answer I dont mind clipping it off at the beginning where it shows that 5 - 0 has a 1 as a carry out of 1, which for a subtract is not an overflow. The long answer because it can be hard to wrap your head around signed vs unsigned and how the adder works in logic in general. The adder does not know or care about signed or unsigned, it does care about add vs subtract, with subtract you invert the second operand, invert the carry in to the lsbit and the carry out of the msbit (think about add, add with carry, sub and sub with carry). The signed vs unsigned takes care if itself (the beauty of twos complement). Reducing the above to an unsigned only discussion makes it more than half as simple as the signed overflow is not (as) obvious (as unsigned overflow) to the casual observer.
I sure hope I cut and pasted the debugged HDL , will get a lot of responses/corrections if I didnt...I spent a few days convincing myself of all of the above and comparing to the results of other processors I had access to, etc. Hopefully this saves you a few days.
Not an expert, but the whole statement on subtraction seems wrong.
You can implement subtraction in two basic ways: directly as subtraction, or as addition of two's complement.
If you go with two's complement addition, then it is as you say: carry of 1 is underflow.
5 - 6
= 0101 - 0110
= 0101 + (1001 + 1)
= 0101 + 1010
= (0)1111, carry 0 = underflow
If you subtract directly, then 1 carry is underflow:
0101 - 0110:
0 to 1 is 1
1 to (1)0 is 1, carry 1
1 + 1 to (1)1 is 1, carry 1
0 + 1 to (1)0 is 1, carry 1 = underflow
There may be other equivalent ways of designing overflow detection units for adders, but the most common is Cin XOR Cout. For example, see the end of lecture 4 http://cs.nyu.edu/~gottlieb/courses/2007-08-fall/arch/class-notes.html
It simply checks if the numbers being added (if something is inverted for 2's complement or not doesn't matter, we look at these values afterwards) carry in to the last digit's calculation but not into the digit beyond the supported bit-size, or the opposite.
This makes sense because if they carry in and not out the result must be negative (since the MSB must be 1) but the operands must be positive (since if they were negative there would be carry out). This is the definition of overflow, since two positives cannot sum to a negative.
This is a signed model however, I'm not sure if that's what you're looking for since you mentioned unsigned. If that's the case, then you're right, the simple addition model has overflow when carry out is 1 (this is equivalent to the above if you consider the addition to have an extra 0 for each operands' MSB, then the carry out will always be 0 and there's overflow iff the carry in is 1. The carry in in this case is the carry out in our model).
Subtraction results in underflow if the value is negative. We can again derive an equivalence if we consider the positive operand to have an appended MSB of 0 and the negative operand one of 1 (sign extension). Then we are negative when the MSB of the result is 1. This happens iff the carry out in our original model (the carry in in the new model) is 0, since only then will the MSB of the result in the new model remain 1.
You example is no exception: 0101 + 1111 + 1 = 0101 with a carry out of 1, and therefore no underflow, since the result is positive.