nested preprocessor directives using backslash for joining lines - system-verilog

Question

systemverilog allows lines to be concatenated with a trailing "\", and this is used very commonly with the tick ("`") preprocessor commands. So the following 2 sets of definitions are identical:
`define A(b) b + \
5
`define A(b) b + 5
Similarly, in the following code, the definitions of X and P are expected to be identical. The only difference is that one version uses the "\" and the other version does not.
`define Y
`define X(a) `ifdef Y \
`define Z a+2 \
$display(`Z); \
`endif
`define P(a) `ifdef Y `define R a+2 $display(`R); `endif
module m();
initial begin
`X(5) // expands as: $display(5+2);
$display(`Z); // expands as: $display(5+2);
`P(7) // expansion was empty, but no error reported
$display(`R); // this reports an error: cyclical definition of R
end
endmodule
But, as the comments mention, one of the versions does not work with the comercial simulators. So my question is: why is the second version wrong, and what exactly are the semantics of "\" for joining consecutive lines, especially in the context of using within `define and other preprocessor commands?

Answer 1

Anything that is written after define is considered as macro name and anything after a space after macro name is considered as macro value/text. The optional formal arguments are delimited with braces as shown below.
text_macro_definition ::= `define text_macro_name macro_text
text_macro_name ::= text_macro_identifier [ ( list_of_formal_arguments
) ]
list_of_formal_arguments ::= formal_argument { , formal_argument }
formal_argument ::= simple_identifier [ = default_text ]
text_macro_identifier ::= identifier
Here, in order to compile successfully, you have to consider define R a+2 as one line and $display as another line. The simulator will not understand by itself that when to end the define macro value and when to start another $display line.
It gets expanded as an assignment and display in a single line:
// Actual expansion
<macro> R = a+2 $display(R);
// Intended expansion
<macro> R = a+2 // assign value to R
$display(R); // then display R
If more than one
line is necessary to specify the text, the newline shall be preceded by a backslash ( \ ).
The issue in this code is that there is no delimiter for the define of R. So R is getting defined as full a+2 $display(R). Now if we add a \, then the simulator understands that it is a new line and hence it considers $display as next statement in compiling.
`define P(a) `ifdef Y `define R a+2 \
$display(`R); `endif
Refer to IEEE 1800-2012 Sntax 22-2 for more information.