How to fix Verilog::VCD::Writer error: Can't locate object method addSignal? - perl

Question

I suspect I made an import error in Perl.
There is a Perl module Verilog::VCD::Writer to write a VCD file. However, when I copy its SYNOPSIS code to have a try, it always raises the error:
Can't locate object method "addSignal" via package
"Verilog::VCD::Writer" at tester.pl line 10.
The SYNOPSIS calls addComment and addModule before addSignal so there should be no problems in my installation.
addSignal is a function defined in Verilog/VCD/Writer/Module.pm, and the other two are defined in Verilog/VCD/Writer.pm. Even I add Verilog::VCD::Writer::Module, still the debugger go to package Writer to find the addSignal method.
If I call the addSignal function in this way:
$writer->Verilog::VCD::Writer::Module::addSignal("TX",7,0);
Can't locate object method "signals_push" via package
"Verilog::VCD::Writer" at
/home/cqsun/lib/perl5/lib/site_perl/5.18.2/Verilog/VCD/Writer/Module.pm
line 41.
Module.pm defined signals_push in a hash, and clearly the debugger didn't find it.
I suspect there is something wrong, but I don't know where it is.
The webpage for this package is http://search.cpan.org/~jvs/Verilog-VCD-Writer-0.002/lib/Verilog/VCD/Writer.pm

Answer 1

This is a documentation bug.
The code in the SYNOPSIS section of the POD has a few problems. The error you see is from the line:
my $TX=$writer->addSignal("TX",7,0); #Add Signals to top
The code used the wrong object handle for the addSignal method. $writer is an object of the Verilog::VCD::Writer module, and it does not have an addSignal method. However, addSignal is a method of the Verilog::VCD::Writer::Module module. The code needs to use $top instead of $writer.
The next line has the same problem:
my $RX=$writer->addSignal("RX",7,0);
Finally, the following line has a syntax error because it is missing the comment delimiter (#) after the semicolon:
my $dut=$top->addModule("DUT"); Create SubModule
Here is a fixed version of the code which runs without errors and generates a VCD output file:
use Verilog::VCD::Writer;
my $writer = Verilog::VCD::Writer->new(timescale=>'1 ns',vcdfile=>"test.vcd");
$writer->addComment("Author:Vijayvithal");
my $top = $writer->addModule("top"); # Create toplevel module
my $TX = $top->addSignal("TX",7,0); #Add Signals to top
my $RX = $top->addSignal("RX",7,0);
my $dut = $writer->addModule("DUT"); #Create SubModule
$dut->dupSignal($TX,"TX",7,0); #Duplicate signals from Top in submodule
$dut->dupSignal($RX,"RX",7,0);
$writer->writeHeaders(); # Output the VCD Header.
$writer->setTime(0); # Time 0
$writer->addValue($TX,0); # Record Transition
$writer->addValue($RX,0);
$writer->setTime(5); # Time 1ns
$writer->addValue($TX,1);
$writer->addValue($RX,0);
I uploaded a patch to the bug report you opened:
https://rt.cpan.org/Ticket/Display.html?id=123724
Also, the Create SubModule comment seems misleading. Perhaps the author intended to use the addSubModule method instead of the addModule method.