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Minimum associativity for a PIPT L1 cache to also be VIPT, accessing a set without translating the index to physical
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Homework question, so please just nudge me in the right direction.
Consider a system with physically-addressed caches, and assume that 40-bit virtual addresses and 32-bit physical addresses are used, and the memory is byte-addressable. Further assume that the cache is 4-way set-associative, the cache line size is 64 Bytes and the total size of the cache is 64 KBytes.
What should be the minimum page size in this system to allow for the overlap of the TLB access and the cache access?
I've been stuck on this question and have no idea how to even begin. Can someone give me a hint towards finding the solution?
I think the most important piece of information in the question is
overlap of the TLB access and the cache access
This means, we access the Cache at the same time we access the TLB. In practice, what we really do is, we index the cache with the index bits from the virtual address and by the time we have located the entry in the cache, we will have the data (physical address) from the TLB. Then we can do the tag comparison with physical address. In other words cache acts as a Virtually indexed, Physically tagged (VIPT) cache.
Even though the scheme sounds efficient, the thing to lookout is, number of bits used to index the cache, cannot be higher than the number of bits needed to represent the page size. Simply, size of a page can put an upper limit on the number of cache entries.
Now coming back to your question,
its a 64KBytes cache with 4 way set assoc. and cacheline of 64Bytes.
Number of cachelines = (64KBytes/4)/64Bytes = 2^8 cachelines
That means if a page is 256Bytes or bigger, we can use this mechanism. If a page is smaller than 256 Bytes, then we cannot assume the index bits of the virtual address and the physical address are going to be the same.
What should be the minimum page size in this system to allow for the
overlap of the TLB access and the cache access?
256Bytes
Related
Given a virtual memory system which utilises a 32-bit virtual address.
A page table that takes 1 MiB of memory per process.
Each PTE(page table entry requires 4 bytes.
The system has a total of 256 Megabytes of memory available.
I understand that a Page table is essentially a list of entries(PTE) that provide a mapping of the virtual addresses to a physical address.
I need to calculate the size of each virtual page. But I have no clue how.
So far all I've got is 2^20(page-table size)/2^2(PTE size)=2^18 this gives me the total amount of entries I can have in a page table. I'm not even sure if this is useful to find the size of each virtual page.
Could anyone point me in the right direction? Perhaps I'm misunderstanding in how these metrics relate to the size of a virtual page.
Edit: I've found out the size of the page is determined by the following.
A virtual address consists of bits for a page pointer and an offset.
The last bits of the virtual address are called the offset which is the location difference between the byte address you want and the start of the page. You require enough bits in the offset to be able to get to any byte in the page.For a 4K page you require (4K == (4 * 1024) == 4096 == 212 ==) 12 bits of offset.
The page pointer can be determined by the number of entries in the table. This was simply my formula from before 2^20(page-table size)/2^2(PTE size)=2^18 entries. Which means I have 18 bits being used in my virtual address for my page pointer. I can determine the offset by 2^32(virtual address size)/2^18 which gives me 2^14. Therefore my page size for my virtual address is 2^14 or 16KiB.
The problem as you describe is under-specified. You need to know the width of the page offset field within the virtual address (or, how many levels of indirection the VM system is using). For example, (as in ONE of the modes that x86 system uses), if you have two levels of indirection, then you will have 10x2 bits used for levels of indirection and remaining 12 bits for offset within the page. That gives you a page size (= frame size) of 4KB.
If you instead use one level of indirection (as ANOTHER x86 mode allowed, but is found less often), then you can have a division of 10 bits for the only level of indirection and remaining 22 bits as offset within the page. That gives a page size of 4MB.
You see above that same 32 bit virtual address can follow different levels of indirection for paging and end up with different page sizes.
Page offset size in the virtual address determines the page size.
There is no answer under those fact. You have the page table entry is 32 bits. That puts a theoretical upper bound on the page size as 2^32. However, some bits are going to used for control so the size will be smaller.
The 1MB size of of the page table and 32-bit virtual address facts are irrelevant to the page size.
I am trying to understand both paradigms of memory management;however, I fail to see the big picture and the difference between both. Paging consists of taking fixed size pages from a secondary to a primary storage in order to do some task requested by a process. Segmentation consists of assigning to each unit in a process an address space, so they are allowed to grow. I don't quiet see how they are related and that's because there are still a lot of holes in my understanding. Can someone fill them up?
I think you have something confused. One problem you have is that the term "segment" had multiple meanings.
Segmentation is a method of memory management. Memory is managed in segments that are of variable or fixed length, depending upon the processor. Segments originated on 16-bit processors as a means to access more than 64K of memory.
On the PDP-11, programmers used segments to map different memory into the 64K address space. At any given time a process could only access 64K of memory but the memory that made up that 64K could change.
The 8086 and it successors used segments with base registers. Each segment could have 64K (that grew with the processors) but a process could have 4 segments (more in later processors).
Paging allows a process to have a larger address space than there is physical memory available.
The 8086's successors used the kludge of paging on top of segments. However, that bit of ugliness has finally gone away in 64-bit mode.
You got your answer right there, paging relates with fixed size pages in a storage while segmentation deals with units in a page. 'Segments' are objects in the class 'Page'
This picture could be found on Operating system concepts, beginning of Chapter 9. The size of virtual address space is 0 to max. My question is:
what will decide the max value? Is it fixed?
what will happen if the hole between stack and heap is filled and one of them of both of them want to grow continually?
I know that my question may be duplicate, but I've read a lot threads and I still cannot get my answer. Thanks in advance!
Keep in mind that what you are seeing is a very simplified diagram of what happens. First of all all, the underlying hardware sets a maximum logical address range.
Some part of that range will be reserved (either through hardware or software, depending upon the processor) for the operating system. The remaining addresses are for the user address space.
So what you are looking at is a conceptual view of a user address space. This can be further limited by system parameters and process quotas.
what will decide the max value? Is it fixed?
Thus MAX is a combination of hardware limits, operating system address allocation, system parameters, and process quotas. It can, therefore, be unfixed.
what will happen if the hole between stack and heap is filled and one of them of both of them want to grow continually?
First of all remember this diagram is only conceptual. One simplification is that the valid addresses within the address space need not be contiguous. There could be holes. Second, memory layout is usually controlled by the linker. The "text" and the "data" can be reversed or even interleaved.
The blue "hole" will generally be unallocated (invalid) memory pages. Some OS's do not grow the stack. It is preallocated by the linked. In a multi-threaded system, there could be multiple stacks (another simplification of the diagram) and there are often multiple heaps.
As various function map pages into the logical address space, the blue area shrinks. If go goes to zero, the next attempt to map pages will fail.
I faced this question in my interview, I answered that, there is no limit, as virtual memory itself imaginary thing, so we don't have any limit.
But I don't understand any proper answer by googling.
Kindly help me out in this and explain the memory limit of virtual memory.
The maximum theoretical size for virtual memory is given by the size of a pointer. The largest number that can be represented by the pointer is the maximum theoretical size of virtual memory. The units are the minimal addressable memory unit (typically bytes).
Real operating systems sometimes impose additional restrictions.
There are a number of restrictions on virtual memory.
The address range of the underlying hardware.
Any subdivisions of the address space. Some ranges may be reserved (for example, System and User address spaces) Some may be invalid altogether. Example: VAX divides the 32-bit address evenly into 2 user spaces, a system space, and a reserved (unusable space).
Limits the operating system imposes on page table size. Must system have a parameter and/or account setting limiting this.
The size of the page file.
I had this problem in an exam today:
Suppose you have a computer system with a 38-bit logical address, page size of 16K, and 4 bytes per page table entry.
How many pages are there in the logical address space? Suppose we use two level paging and each page table can fit completely in a frame.
For the above mentioned system, give the breakup of logical address bits clearly indicating number of offset bits, page table index bits and page directory index bits.
Suppose we have a 32MB program such that the entire program and all necessary page tables (using two level paging) are in memory. How much memory (in number of frames) is used by the program, including its page tables?
How do I go about solving such a problem? Until now I would have thought page size = frame size, but that won't happen in this case.
Here is what I think:
Since the page size is 16K, my offset will be 17 bits (2^17 = 16K). Now how do I divide the rest of the bits, and what will be the frame size? Do I divide the rest of the bits in half?
238 / 16384 = 16777216 pages.
On one hand, the remaining 38-log216384=24 bits of address may be reasonable to divide equally between the page directory and page table portions of the logical address since such a symmetry will simplify the design. On the other hand, each page table should have the same size as a page so they can be offloaded to the disk in exactly the same way as normal/leaf pages containing program code and data. Fortunately, in this case using 12 bits for page directory indices and page table indices gets us both since 212 * 4 bytes of page table entry size = 16384. Also, since a page address always has 14 least significant bits set to zero due to the natural page alignment, only 38-14=24 bits of the page address need to be stored in a page table entry and that gives you 32-24=8 bits for the rest of control data (present, supervisor/user, writable/non-writable, dirty, accessed, etc bits). This is what we get assuming that the physical address is also not longer than 38 bits. The system may have slightly more than 38 bits of the physical address at the expense of having fewer control bits. Anyway, everything fits. So, there, 38=12(page directory index)+12(page table index)+14(offset).
32MB/16KB = 2048 pages for the program itself. Each page table covers 212=4096 pages, so you will need about 2048/4096=0 page tables for this program. We round this up to 1 page table. Then there's also the page directory. 2048+1+1=2050 is how many pages are necessary to contain the entire program with its related pages tables in the memory.