What is the purpose of "new" on the function in Systemverilog? - system-verilog

Question

I'm trying to understand systemverilog, So I'm referring this site.
But I'm confused the usage of "new" in the below code.
class packet;
//class properties
bit [31:0] addr;
bit [31:0] data;
bit write;
string pkt_type;
//constructor
function new(bit [31:0] addr,data,bit write,string pkt_type);
addr = addr;
data = data;
write = write;
pkt_type = pkt_type;
endfunction
//method to display class prperties
function void display();
$display("---------------------------------------------------------");
$display("\t addr = %0h",addr);
$display("\t data = %0h",data);
$display("\t write = %0h",write);
$display("\t pkt_type = %0s",pkt_type);
$display("---------------------------------------------------------");
endfunction
endclass
module sv_constructor;
packet pkt;
initial begin
pkt = new(32'h10,32'hFF,1,"GOOD_PKT");
pkt.display();
end
endmodule
Especially, you can see the
function new(bit [31:0] addr,data,bit write,string pkt_type);
addr = addr;
data = data;
write = write;
pkt_type = pkt_type;
endfunction
This code used "new".
I'm confused that what does "new" mean in function ~ endfunction?
What purpose the "new" used in function block?
As you can see that another block in the above code,
function void display();
$display("---------------------------------------------------------");
$display("\t addr = %0h",addr);
$display("\t data = %0h",data);
$display("\t write = %0h",write);
$display("\t pkt_type = %0s",pkt_type);
$display("---------------------------------------------------------");
endfunction
There is no "new" used in function block.
Would you help me let me know what does it mean?
update,
I've seen a duplicate of another question.
But I've one query about Dave's answer.
If you do not declare a function new() inside your class, SystemVerilog defines an implicit one for you. The reason you might want to declare a function new inside your class is if you want to pass in arguments to the constructor, or you have something that requires more complex procedural code to initialize.
Especially,
If you do not declare a function new() inside your class, SystemVerilog defines an implicit one for you.
Would you please help me for understanding what does "an implicit one for you" with any simple example?
I've got one more experiment as the below,
class packet;
//class properties
bit [31:0] addr;
bit [31:0] data;
bit write;
string pkt_type;
//constructor
function temp(bit [31:0] addr1,data1,bit write1,string pkt_type1);
addr = addr1;
data = data1;
write = write1;
pkt_type = pkt_type1;
endfunction
//method to display class prperties
function void display();
$display("---------------------------------------------------------");
$display("\t addr = %0h",addr);
$display("\t data = %0h",data);
$display("\t write = %0h",write);
$display("\t pkt_type = %0s",pkt_type);
$display("---------------------------------------------------------");
endfunction
endclass
module sv_constructor;
initial begin
packet pkt;
packet temp;
pkt = new();//32'h10,32'hFF,1,"GOOD_PKT");
temp = new();
pkt.addr = 1;
pkt.display();
end
endmodule
As you can see that code there is no "new" in temp function. so I'm confused that which case do I need "new" in function?
update
If I want to make a custom function such as the below,
class MyClass;
int number;
function custom_function1();
number = 0;
endfunction
function custom_function2 (int num);
number = num;
endfunction
endclass
Can't I have just a like that?
update 2
class MyClass;
int number;
function new();
number = 0;
endfunction
function new (int num);
number = num;
endfunction
function new (int num);
number = num;
endfunction
function new (int temp);
number = temp;
endfunction
endfunction
endclass
If we make above MyClass, then how do we know which function is called?

Answer 1

System verilog test bench implements Object Oriented Programming model.
A class is the definition of the object.
class MyClass;
members....
function new();
// do something
endfunction
endclass
The new function in the class is a constructor which gets called at the time of the object instantiation.
A class could be instantiated in the following way:
MyClass a_class = new();
The call to the new() function in this case creates an object of type MyClass, calls its member function new and makes a_class a reference to the newly created object.
System verilog does not support function overloading, there fore only a single constructor can be used. However one can use default argument values to add some flexibility
class MyClass;
int number;
function new (int num = 0);
number = num;
endfunction
endclass
In the above case you can use the constructor to create a version of the object you are interested in:
MyClass a_class = new(); // will assign '0' to the 'number'
MyClass b_class = new(3); // will call the second constructor and assign '3'

Answer 2

new() is the special function in SystemVerilog to construct an object, also known as constructor. It does not have any return type.