Why do I need an abstract class in systemverilog? - system-verilog

Question

I came across about abstract class in systemverilog when I googling.
But I didn't get it exactly why do we need about abstract class in systemverilog.
So Would you please help me to understand about abstract class in system verilog? Why do we need it, when do we need it.

Answer 1

An abstract class is designed to be extended and cannot be instantiated. Abstract classes are useful to define a contract for extended classes (i.e. extended classes must implement specific functions) in addition to providing existing functionality that can be reused or overridden. pure virtual functions are un-implemented in an abstract class, but must be implemented in extended classes (forming a contract).
Example:
virtual class animal;
// Implemented functionality that can be overridden in extended classes or used as-is
virtual function int get_legs();
return 4;
endfunction
// Functions that must be implemented by extended classes
pure virtual function string get_sound();
pure virtual function string get_name();
endclass
class cat extends animal;
virtual function string get_sound();
return "meow";
endfunction
virtual function string get_name();
return "Mog";
endfunction
endclass
class dog extends animal;
virtual function string get_sound();
return "woof";
endfunction
virtual function string get_name();
return "Rover";
endfunction
endclass
class duck extends animal;
// override default functionality
virtual function int get_legs();
return 2;
endfunction
virtual function string get_sound();
return "quack";
endfunction
virtual function string get_name();
return "Feathers";
endfunction
endclass
module my_module;
initial begin
animal animals[$];
cat c;
dog d;
duck du;
c = new();
d = new();
du = new();
animals.push_back(c);
animals.push_back(d);
animals.push_back(du);
foreach(animals[a])
begin
$display("%s has %0d legs and makes the sound %s",
animals[a].get_name(), animals[a].get_legs(), animals[a].get_sound());
end
end
endmodule
If you are using UVM, uvm_subscriber is a SystemVerilog example of an abstract class (where the write function must be implemented in extended classes).