Trying to do this
parameter integer PRECHARGE_CLOCKS = $ceil(PRECHARGE_NS / CLOCK_PERIOD_NS);
And then use the value in a comparion
if(InitPrechargeCounter < PRECHARGE_CLOCKS - 1)
But getting this error
Error (10174): Verilog HDL Unsupported Feature error at Ram.sv(23): system function "$ceil" is not supported for synthesis
Is there a way around this so that I get the value calculated at compile time?
Using some different language construct instead of parameter?
Try this:
parameter integer PRECHARGE_CLOCKS = ((PRECHARGE_NS + CLOCK_PERIOD_NS -1) / CLOCK_PERIOD_NS);
It should round up as what $ceil does.
I ended up working around this with the following macro, this creates 2 extra parameters for the sake of rounding up, but this is the best solution I've found so far.
This is not limited to integer arguments and works with real numbers.
I've tested this with Quartus and Modelsim
`define Ceil(ParamName, Expression) \
parameter ParamName``_F = Expression;\
parameter integer ParamName``_R = ParamName``_F;\
parameter integer ParamName = (ParamName``_R == ParamName``_F || ParamName``_R > ParamName``_F) ? ParamName``_R : (ParamName``_R + 1);
And then instead of
parameter integer AUTOREFRESH_CLOCKS = $ceil(UTOREFRESH_NS/CLOCK_PERIOD_NS);
You would invoke the macro
`Ceil(AUTOREFRESH_CLOCKS, UTOREFRESH_NS/CLOCK_PERIOD_NS)
And this is not both synthesizable in Quartus and works in Modelsim
Related
I need to convert a Long number as Fixed point into a Double rappresentation.
The fixed point math is used into the synthesis process and the Real data type only for validation and simulation.
If I make multiple convertion in chain with multiple datatypes to adjust the format then it is not enough or completely wrong .
In my case with a fixed point mantissa of 44 bit I have 3bit integer+sign bit. Q notation like "sfix_44_48"
As example I am doing this to convert a fixed point integer number into a Real value(getting the number 0.5f ):
logic signed [47:0] fp_number = 48'h0800_0000_0000; // it should be 0.5f
real r_val;
real rr_val;
real rrr_val;
real tmp;
initial
begin
r_val = $itor(fp_number)/(2**44); // doesn't solve the problem.
rr_val = real'{fp_number}/(2**44); // doesn't solve the problem.
$cast(tmp,fp_number>>>44); // doesn't solve the problem
rrr_val = tmp;
end
$itor(...) is limited to 32bit integer part.
As result of above I get zero or NaN, on Modelsim simulation.
No luck during all these convertions.
the SV LRM doesn't seem to have a clear way to do this convertion.
What is the SV workaround to allow simulations to analize data greater than 32bit size easily? please.
C.
You want to use
rr_val = real'(fp_number)/(2.0**44);
Do not use any of the $TtoT functions from Verilog. They have fixed datatype inputs and outputs.
2**44 gets computed as a 32-bit 2-complement value and overflows, giving you 0. You can use 2.0 or real'(2) instead.
thanks to #dave_59 I post this piece of code which show the mess with the convertion.
logic signed [47:0] fp_number = 48'h0800_0000_0000; // it should be 0.5f
logic signed [31:0] fp_number2 = 32'h0800_0000; // it should be 0.5f
real r_val;
real rr_val;
real rrr_val;
real rrrr_val;
initial
begin
$display("48bit fp convertion sfix_44_48");
r_val = real'{fp_number}/(2**44); // doesn't solve the problem (curly braces valid sintax but wrong convertion + wrong convertion on the denominator).
rr_val = real'{fp_number}/(2.0**44); // doesn't solve the problem (curly braces valid sintax but wrong convertion + denominator convertion OK).
rrr_val = real'(fp_number)/(2**44); // doesn't solve the problem (numerator OK + the power operation is not properly converted to a Real number as result).
rrrr_val = real'(fp_number)/(2.0**44); // solve the problem with long integer fixed points convertion (the braces are not curly anymore).
$display("r_val[%08f]",r_val,", rr_val[%08f]",rr_val,", rrr_val[%08f]",rrr_val,", rrrr_val[%08f]",rrrr_val); // it should be 0.5 on the fourth data
$display("32bit fp convertion sfix_28_32");
r_val = real'{fp_number2}/(2**28); // result totally different than previous 48bit operation, doesn't solve the problem (curly braces valid sintax but wrong convertion + wrong convertion on the denominator).
rr_val = real'{fp_number2}/(2.0**28); // doesn't solve the problem (curly braces valid sintax but wrong convertion + denominator convertion OK).
rrr_val = real'(fp_number2)/(2**28); // with a 32bit range it apparently solve the problem (numerator OK + the power operation is OK with this range).
rrrr_val = real'(fp_number2)/(2.0**28); // solve the problem with long integer fixed points convertion (the braces are not curly anymore).
$display("r_val[%08f]",r_val,", rr_val[%08f]",rr_val,", rrr_val[%08f]",rrr_val,", rrrr_val[%08f]",rrrr_val); // it should be 0.5 on the fourth data
end
the only valid convertion at 48bit is the fourth case.
For 32bit the third case is valid and also the fourth case.
First: the classic pow(...) operation must be done with this syntax (2.0**BIT) which will create a Real division and not a integer division using (2**BIT) when a scaling fixed point will be applied.
In this case the operation above is managed as float/double(C style) or real(SystemVerilog)
* Second: the real'() cast operation MUST be used with NO curly braces.
I didn't have a Linting tool to proper check the syntax so I would expect a Warning due to the validity of the operation with the curly braces.
Third: the subdle results are ok if the INTEGER denominator is limited at 32bit operations.
As results shown below:
SIM START.
# 48bit fp convertion sfix_44_48
# ** Error (suppressible): (vsim-8604) ./blocks/sim/test_tb.sv(141): NaN (not a number) resulted from a division operation.
# ** Error (suppressible): (vsim-8630) Infinity results from division operation.
# Time: 0 ps Iteration: 0 Process: /test_tb/#INITIAL#138 File: ./blocks/sim/test_tb.sv Line: 143
# r_val[-1.#IND00], rr_val[0.000000], rrr_val[1.#INF00], rrrr_val[0.500000]
# 32bit fp convertion sfix_28_32
SIM END.
# r_val[0.000000], rr_val[0.000000], rrr_val[0.500000], rrrr_val[0.500000]
The solution is to avoid any not protected casting, like a casting with the braces boundary:
r_val = real'{ byteU,byteH,byteL} / (2.0**44) ; // WRONG
rr_val = real'({byteU,byteH,byteL}) / (2.0**44) ; // CORRECT
If the scaling factor occurs then the operation, generally /, must be done with the same type of operands (real/real).
Unsafe way is (real/long) which leads into a nightmare.
Is it possible (and if so how) to use an objective function that has a conditional expression?
Changing the example from the docs, I would like an expression like:
def objective_function(model):
return model.x[0] if model.x[1] < const else model.x[2]
model.Obj = Objective(rule=objective_function, sense=maximize)
Can this be modelled directly like this or do I have to consider some sort of transformation (and if so how would this look like)?
Just executing the above gives an error message like:
Evaluating Pyomo variables in a Boolean context, e.g.
if expression <= 5:
is generally invalid. If you want to obtain the Boolean value of the
expression based on the current variable values, explicitly evaluate the
expression using the value() function:
if value(expression) <= 5:
or
if value(expression <= 5):
which I think is because Pyomo thinks I'd like to obtain a value, instead of an expression with the variable.
One way to formulate that is by using a logical disjunction. You can look into the Pyomo.GDP documentation for usage, but it would look like:
m.helper_var = Var()
m.obj = Objective(expr=m.helper_var)
m.lessthan = Disjunct()
m.lessthan.linker = Constraint(expr=m.helper_var == m.x[0])
m.lessthan.constr = Constraint(expr=m.x[1] < const)
m.greaterthan = Disjunct()
m.greaterthan.linker = Constraint(expr=m.helper_var == m.x[2])
m.greaterthan.constr = Constraint(expr=m.x[1] >= const)
m.lessthanorgreaterthan = Disjunction(expr=[m.lessthan, m.greaterthan])
# some kind of transformation (convex hull or big-M)
You can also formulate this using complementarity constraints.
This code fails:
let element: Float = self.getElement(row: 1, column: j)
let multiplier = powf(-1, j+2)*element
with this error:
Playground execution failed: :140:51: error: cannot invoke '*' with an argument list of type '(Float, Float)'
let multiplier = powf(-1, j+2)*element
Bear in mind that this occurs in this block:
for j in 0...self.columnCount {
where columnCount is a Float. Also, the first line does execute and so the getElement method indeed returns a Float.
I am completely puzzled by this as I see no reason why it shouldn't work.
There is no implicit numeric conversion in swift, so you have to do explicit conversion when dealing with different types and/or when the expected type is different than the result of the expression.
In your case, j is an Int whereas powf expects a Float, so it must be converted as follows:
let multiplier = powf(-1, Float(j)+2)*element
Note that the 2 literal, although usually considered an integer, is automatically inferred a Float type by the compiler, so in that case an explicit conversion is not required.
I ended up solving this by using Float(j) instead of j when calling powf(). Evidently, j cannot be implicitly converted to a Float.
I was trying to return type std_logic_vector by type conversion in vhdl.
Here is my code:
function mul(num1,num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector is
variable v_TEST_VARIABLE1 : integer;
variable v_TEST_VARIABLE2 : integer;
variable n_times: integer:=1;
variable product: integer:=0;
begin
for n_times in 1 to v_TEST_VARIABLE2 loop
product:=product + v_TEST_VARIABLE1;
end loop;
return std_logic_vector(product);
end mul;
It gives "Illegal type conversion from std.standard.integer to ieee.std_logic_1164.std_logic_vector (numeric to array)." on compilation.
How do I return std_logic_vector in such a code?
See Russell's post first. If you use the VHDL-2008, numeric_std_unsigned package, then you can use just one conversion:
use ieee.numeric_std_unsigned.all ;
...
return to_std_logic_vector(product, length) ; -- long form
-- alternate short form
return to_slv(product, length) ;
Usage warning: for synthesis, I consider VHDL-2008 items to be on the bleeding edge of support. Hence, while I use VHDL-2008 frequently in my testbenches, I try to limit the usage of it in my RTL code to what can't be done using other methods. However, if you ever want to use code like this, it is it is important to try it out in your synthesis tool and submit a bug report against it if it does not work - that is the only way change happens.
You must first convert it to an unsigned. I hope you're using numeric_std? If so, your code looks like this. Note that to use to_unsigned you must know the length of your output std_logic_vector. So this either needs to be an input to your function or you can bound the return vector:
return std_logic_vector(to_unsigned(product, length));
More information about how to convert std_logic_vector to integer.
I am trying to perform a modulo operation in MATLAB, and I'm not sure how to convert the input variable to the correct data type for the modulo operation to complete.
Here is what I have:
sequence = 0;
....
sequence = sequence + 1;
if (modp(sequence, 3) == 0)
....
In C-ish, I'm looking to perform if (sequence % 3 == 0).
MATLAB complains that there is no modp operation for a double, and that I must use an int. However, the documentation doesn't say which integer format I need to use (i.e., int8, int64, et cetera) and none of those integer formats work.
What am I doing wrong?
Did you realize you are using a function of the "symbolic toolbox"? I don't see any advantage in this case thus simply use mod(a,b) from Matlab (there is also a fixed point mod(a,b) and symbolic mod(a,b), don't confuse them)
http://www.mathworks.de/de/help/matlab/ref/mod.html