SystemVerilog covergroup include coverpoint based on parameter - system-verilog

Question

I'm creating coverage for my design and I want to reuse a covergroup definition for multiple instances. The first instance should use all of the coverpoints as intended, but for the second instance, I want to exclude some of the coverpoints in the covergroup.
I was thinking I could use an input to the covergroup and iff () the unwanted coverpoints such that the first instance ties the input to 1 and the second instance ties the input to 0. However I think this will still show the coverpoints for the second instance as always not hit, and I want them to not be included at all.
covergroup cg_address(input bit enable) # (posedge clock);
address_check: coverpoint (address){
bins addr_0 = {5'd0};
bins addr_1 = {5'd1};
}
data_check: coverpoint (data) iff (enable){
bins data_0 = {10'd0};
bins data_1 = {10'd1};
}
endgroup : cg_address
cg_address cg_address_inst0 = new(1'b1);
cg_address cg_address_inst1 = new(1'b0); //want this one to exclude data_check coverpoint
I know the above code won't work because the second instance will still have the data_check coverpoint, it will just never hit either bin because the enable is tied to 0. Is there any other way I can try to exclude the data_check coverpoint for the second instance?

Answer 1

You need to do two things:
Set the weight of the coverpoint to 0.
Turn on option.per_instance = 1; for the covergroup.
For example:
covergroup cg_address(input bit enable) # (posedge clock);
option.per_instance = 1;
address_check: coverpoint (address){
bins addr_0 = {5'd0};
bins addr_1 = {5'd1};
}
data_check: coverpoint (data) {
option.weight = enable;
bins data_0 = {10'd0};
bins data_1 = {10'd1};
}
endgroup : cg_address
cg_address cg_address_inst0 = new(1);
cg_address cg_address_inst1 = new(0); //want this one to exclude data_check coverpoint