I am trying to bring up one of the ADC's on the STM32L476 Nucleo board. I think i have things configured ok, but i must be missing a step. I know this can be done use the HAL API and CubeMX, but i prefer register level access when bringing up a new board. Here is my code - i think it's commented to enough so it can be understood. I stripped out the rest of the code to keep it simple.
The problem i don't understand is that when the code starts the while loop - the ADC is not ready - that is the ADC1->ISR[0] is not set - and does not get set. I have confirmed the bits are set where i think they should be using keil.
Can anyone spot what is missing?
#include <stm32l4xx.h>
#include <stdio.h>
#ifdef __cplusplus
extern "C"
#endif
int main(void)
{
uint32_t adcResult = 0;
/* Configure the clocks - using MSI as SYSCLK #16MHz */
RCC->CR &= 0xFFFFFF07; //Clear ~MSIRANGE bits and MSIRGSEL bit
RCC->CR |= 0x00000089; //Set MSI to 16MHz and MSIRGSEL bit
char *dataPtr = NULL;
//init ADC1
ADC1->CR &= 0xDFFFFFFF; //Take ADC out of deep power down - i break at this point to allow enough time - doesn't help
ADC1->CR |= 0x10000000; //Enable ADC1 votage regulator
RCC->AHB2ENR |= 0x00002001; //Enable the ADC clock, and GPIOA clk
GPIOA->ASCR |= 0x00000001; //Connect analog switch to GPIOA[0]
GPIOA->MODER |= 0x00000003; //Set A0 for analog input mode
ADC1->ISR |= 0x00000001; //Clear the ADRDY bit in the ADCx_ISR register by writing ‘1’.
ADC1->SQR1 |= 0x00000040; //Set for a sequence of 1 conversion on CH0
while (1)
{
ADC1->CR |= 0x00000004; //Convst
while(!(ADC1->ISR & 0x4));
adcResult = ADC1->DR;
sprintf(dataPtr, "%d", adcResult);
}
}
I solved this - finally. If anyone gets into the same place. I had set the SYSCLK as the ADC clock source, but this needs to be setup in RCC->CCIPR[29:28].
It's the little things...
Related
I am adapting this bootloader for STM32F373CC to my device. To indicate that the device is powered but in bootloader mode, I'd like to turn on some of the status LEDs. However, this bootloader doesn't use the STM Cube MX libraries, so I have to code it low-level. The header file stm32f373xc.h is included, so I can use expressions like GPIOB_BASE.
I tried the following first thing in main(), but unfortunately it doesn't work:
// turn on GPIOB clock: SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);
uint32_t* rcc = (uint32_t*)RCC_BASE;
*(rcc+0x14) |= RCC_AHBENR_GPIOBEN; // AHBENR is at offset 0x14
// configure Port B, pins 4 and 5 to GPIO, Open Drain, low.
uint32_t* gpiob = (uint32_t*)GPIOB_BASE;
*(gpiob) |= 0x500; // GPIO output mode --- GPIOB_MODER = 0x500; (bits 11:8 = 0101), offset 0
*(gpiob) &= ~0xA00;
*(gpiob+0x04) |= 0x30; // output type open drain --- GPIOB_OTYPER = 0x30; (bits 5:4 = 11), offset 0x04
*(gpiob+0x0c) &= ~0xF00; // pull up/down off --- GPIOB_PUPDR = 0x0; (bits 11:8 = 0000), offset 0x0c
*(gpiob+0x14) &= ~0x30; // output low --- GPIOB_ODR = 0x0; (bits 5:4 = 00), offset 0x14
Any ideas what I'm missing? How can I find out if the problem is the clocking of the Port B, or the pin configuration?
I found this similar post, but the first answer requires the entire CMSIS, and the second answer lacks comments, so I don't fully understand what they are doing.
I hope that you know that open-drain outputs require pull-up (internal or external)
Use CMSIS definitions, not magic numbers and operations.
requires the entire CMSIS
And what is the problem? CMSIS does not add any overhead to your code, only handy definitions and inline functions, which do not change the size of the code if not used.
Also, HAL has very handy macros useful even if you do not use HAL library itself (it also will not increase the code size even by a single byte)
I will not check your magic offsets and numbers.
First error: after enabling the peripheral clock you need to wait. It is described in the Reference Manual. You do not wait and your first MODER operation has no effect. HAL macros read back the register to make sure that the operation has completed.
Example from STM32L4:
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
UNUSED(tmpreg); \
} while(0)
Then use the CMSIS registers typedefs and definitions.
#define PIN4 4
#define PIN5 5
GPIOB -> MODER &= ~((0b11 << (2 * PIN5)) | (0b11 << (2 * PIN4)));
GPIOB -> MODER |= ((0b01 << (2 * PIN5)) | (0b01 << (2 * PIN4)));
GPIOB -> OTYPER &= ~((1 << PIN4) | (1 << PIN5));
GPIOB -> OTYPER |= (1 << PIN4) | (1 << PIN5);
GPIOB -> BSRR = (1 << (PIN4 + 16)) | (1 << (PIN5 + 16)); // set the pins low
I'm using the stm32f767zi, and I'm trying to send test data over the USART peripheral. I've done the same configuration as I always do on any device, but this time it does not output anything... I cannot find the mistake, can someone help ?
The clock setup
// Enables TIM8 (Delay), USART1 (STDOUT)
RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN
| RCC_APB2ENR_USART1EN);
// Enables GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, DMA1
RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN
| RCC_AHB1ENR_GPIOBEN
| RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIODEN
| RCC_AHB1ENR_GPIOEEN
| RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_DMA1EN);
The initialization code
// Makes A8 (TX) and A9 (RX) Alternative Function
GPIOA->MODER &= ~(GPIO_MODER_MODER8_Msk
| GPIO_MODER_MODER9_Msk);
GPIOA->MODER |= ((0x2 << GPIO_MODER_MODER8_Pos)
| (0x2 << GPIO_MODER_MODER9_Pos));
// Selects AF7 for both A8 (TX) and A9 (RX).
GPIOA->AFR[1] &= ~(GPIO_AFRH_AFRH0_Msk
| GPIO_AFRH_AFRH1_Msk);
GPIOA->AFR[1] |= ((7 << GPIO_AFRH_AFRH0_Pos)
| (7 << GPIO_AFRH_AFRH1_Pos));
// Selects very high speed for A8 (TX) and A9 (RX)
GPIOA->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR8_Msk
| GPIO_OSPEEDR_OSPEEDR9_Msk);
GPIOA->OSPEEDR |= ((0x3 << GPIO_OSPEEDR_OSPEEDR8_Pos)
| (0x3 << GPIO_OSPEEDR_OSPEEDR9_Pos));
// Calculates and sets the baud rate.
m_USART->BRR = (((2 * clk) + baud) / (2 * baud));
// Configures the USART peripheral further.
m_USART->CR1 = USART_CR1_TE // Transmit Enable
| USART_CR1_RE // Receive Enable
| USART_CR1_UE; // USART Enable (EN)
and the write function:
*reinterpret_cast<uint8_t *>(m_USART->TDR) = c;
while (!(m_USART->ISR & USART_ISR_TC));
The problem you have is that you set the wrong pins. It should be PA9 & PA10
your write is also wrong
it should be :
*reinterpret_cast<volatile uint8_t *>(&m_USART->TDR) = c;
or C style:
*(volatile uint8_t *)(&m_USART->TDR) = c;
you are also checking the wrong flag.
TC is important if you want to disable the peripheral after the transition. In normal conditions use TXE flag instead.
while (!(m_USART->ISR & USART_ISR_TXE));
Your reinterpret_cast is unnecessary and incorrect.
I assume you actually wrote *reinterpret_cast<uint8_t *>(&m_USART->TDR) = c; but that is still wrong.
The person who wrote the standard device header has taken great care to make sure that USARTx->TDR already has the correct type, I strongly advise you to trust them and not cast it! In this particular case they will have made it volatile, and you have not, so it is possible that the compiler thinks it can make an optimization by not bothering to perform a write to something that you never read back.
The reason you probably got away with this on other STM32 parts is that their UARTs have just DR for both transmit and receive so reading DR for reception made the compiler think it couldn't eliminate the write.
Also, I don't know about this part, but many STM32 need an extra cycle between writing to RCC->xxxENR and using the respective peripheral, this is usually done with a read of the same register, eg:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
(void)RCC->AHB1ENR;
// now safe to access GPIOA registers
I'm currently having problem with RTC clock (LSE) on STM32L433.
When Vdd is supplied and rtc configured clock is working as expected.
As soon as i remove vdd (vbat provided by coin cell) lse crystal stops oscillating hence rtc problem but backup registers are preserved time is frozen for vdd off period.
What could be cause of the problem? is there any pwr register that i'm missing?
Thanks for response in advance.
RTC setup code (library for registers is libopencm3)
void rtc_setup(time_struct time, date_struct date)
{
usart_puts("1\n");
rtc_wkup_set = false;
/* cause a backup domain reset to select the clock source for RTC */
RCC_BDCR |= RCC_BDCR_BDRST;
RCC_BDCR &= ~RCC_BDCR_BDRST;
pwr_disable_backup_domain_write_protect();
RCC_BDCR &= ~(RCC_BDCR_RTCSEL_MASK << RCC_BDCR_RTCSEL_SHIFT);
RCC_BDCR |= RCC_BDCR_RTCEN | (RCC_BDCR_RTCSEL_LSE << RCC_BDCR_RTCSEL_SHIFT) | (RCC_BDCR_LSEDRV_SHIFT << RCC_BDCR_LSEDRV_HIGH) | RCC_BDCR_LSEON;
//TODO: Add timeout for RTC FAIL
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0)
;
usart_puts("2\n");
/* enable RTC */
rtc_unlock();
RTC_ISR |= RTC_ISR_INIT;
while (!(RTC_ISR & RTC_ISR_INITF))
;
RTC_CR &= ~(RTC_CR_FMT);
RTC_DR = (uint32_t)date;
RTC_TR = (uint32_t)time;
RTC_ISR &= ~(RTC_ISR_INIT);
usart_puts("3\n");
rtc_lock();
}
Issue was short on one of the legs of stm due to flux residue.
Issue solved
I'm trying to use the I2C interface of the STM32F3 Nucleo-Board to communicate with a EEPROM.
Unfortunately I don't have a clock signal.
I tried to get a clock signal by setting the bits in the registers and also by using CubeMX. Both times I've got the same result: no clock signal.
Thanks for your help!
Here my code...
void I2C_Init(void){
RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
GPIOA->MODER |= GPIO_MODER_MODER15_1;
GPIOA->MODER &= ~GPIO_MODER_MODER15_0; //AF
GPIOB->MODER |= GPIO_MODER_MODER7_1;
GPIOB->MODER &= ~GPIO_MODER_MODER7_0; //AF
GPIOA->OTYPER |= GPIO_OTYPER_OT_15;
GPIOB->OTYPER |= GPIO_OTYPER_OT_7; //Open drain
GPIOA->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1); //speed high
GPIOB->OSPEEDR |= (GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1);
GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR15_0 | GPIO_PUPDR_PUPDR15_1);
GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR7_0 | GPIO_PUPDR_PUPDR_1); //no pull -> external pull up resistor used
PA15_AF4();
PB7_AF4(); //alternate function 4 used
RCC->CFGR3 |= (1<<I2C1SW); //SYSCLK
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; //clock enable
I2C1->TIMINGR = 0x10707DBC; //with CubeMX
I2C1->CR1 |= I2C_CR1_PE; //peripheral enable
}
I use PA15 for SCL and PB7 for SDA.
I2C will only generate a clock on the line if it is sending or expecting data. Try sending data and then using a scope to probe the data and clock line.
I try to make master and slave stm32f103 (bluepills) communicate. But I am having trouble with receiving. When I connect my master to logic analyser I can see MOSI as in the picture
Logic Analyser
In the picture, MOSI is sending "Y" letter. But not all clock pulses same.(I don't know if this is the reason of communication fail)
here is my schematics and my code I simplified as much as I can.
Master Code:
int i;
RCC ->APB2ENR |= 0x00001004; //SPI1,GPIOA clock en
GPIOA ->CRL &= 0x00000000;
GPIOA ->CRL |= 0xb0b33333;
SPI1->CR1 = SPI_CR1_SSM| SPI_CR1_SSI| SPI_CR1_MSTR|SPI_CR1_BR_2;
SPI1->CR1 |= SPI_CR1_SPE; // enable SPI
while(1){
SPI1 -> DR = 'A';
for(int i = 0 ;i<400000;i++);
while( !(SPI1->SR & SPI_SR_TXE) ); // wait until transmit buffer empty
}
and Slave
int i;
RCC ->APB2ENR |= 0x0000100c; //SPI1,GPIOA,GPIOB clock en
GPIOB ->CRH &= 0x00000000;
GPIOB ->CRH |= 0x33333333;
GPIOA ->CRL &= 0x00000000;
GPIOA ->CRL |= 0x4b443333;
GPIOA ->CRH &= 0x00000000;
GPIOA ->CRH |= 0x33333333;
SPI1->CR1 = SPI_CR1_SSM| SPI_CR1_SSI| SPI_CR1_BR_2;
SPI1->CR1 |= SPI_CR1_SPE; // enable SPI
SPI1->CR1 &=~SPI_CR1_MSTR; //disable master
for(int c=0;c<5;c++){
LCD_INIT(cmd[c]);
}
while(1){
while( !(SPI1->SR & SPI_SR_RXNE));
char a = SPI1 ->DR;
for (i=0;i<400000;i++);
LCD_DATA(a);
for (i=0;i<400000;i++);
}
}
My Schematic:
Schematic
The problem is slave is not receiving any data.
It stucks in the loop while( !(SPI1->SR & SPI_SR_RXNE));
First, what are your HCLK and APB2 bus frequencies? If I'm not mistaken, you seem to use (fPLCK / 32) for SPI clock and your logic analyzer shows ~2 or 3 MHz clock. If your APB2 frequency is higher than the 72 MHz limit, you may experience clock problems.
In the slave, you use SSM (software slave management) and activate SSI (internal slave select). The name of the SSI bit is misleading: It mimics the physical NSS pin. So when SSI = 1, the slave is not selected. This is probably the reason why the slave ignores the incoming bytes.