I am creating UVM VIP which is able to switch its clock polarity. Clocking block is used in the interface.
For example, a monitor should sample the data using posedge or negedge of incoming clock depending on UVM configuration - and this polarity change can happen on the fly.
This can be implemented as follows:
// In the interface, two clocking blocks are defined
// one for posedge (passive_cb), one for negedge (passive_cbn).
task wait_clock_event();
if (cfg.pol == 0) #vif.passive_cb;
else #vif.passive_cbn;
endtask
task sample_data();
if (cfg.pol == 0) pkt.data = vif.passive_cb.data;
else pkt.data = vif.passive_cbn.data;
endtask
task run();
wait_clock_event();
sample_data();
endtask
This seems to work but waste code lines and prone to error.
Is there any better solution?
Assuming the monitor has exclusive access to the clocking block, you could consider modifying clocking event in the interface with the iff qualifier.
bit pol;
clocking passive_cb #(posedge clk iff !pol, negedge clk iff pol);
input data;
endclocking
There is a potential race condition if pol changes in the same timestep as the target clock polarity.
Your monitor code would then include a set function and other tasks can be simplified to us only one clocking block.
function void set_vifcb_pol();
vif.pol = cfg.pol;
endfunction
task wait_clock_event();
#vif.passive_cb;
endtask
task sample_data();
pkt.data = vif.passive_cb.data;
endtask
task run();
set_vifcb_pol();
wait_clock_event();
sample_data();
endtask
Related
Clocking block input signal data_rvalid_i can not be driven.
CB_CODE:
default clocking response_driver_cb #(posedge clk);
input reset;
output data_req_o;
input data_gnt_i;
output data_addr_o;
output data_we_o;
output data_be_o;
input data_rvalid_i;
output data_wdata_o;
input data_rdata_i;
input data_err_i;
endclocking
Driver Patch Code:
task reset_signals();
`DRIVER_IF.data_rvalid_i <= 1'b0;
`DRIVER_IF.data_gnt_i <= 1'b0;
`DRIVER_IF.data_rdata_i <= 'b0;
`DRIVER_IF.data_err_i <= 1'b0;
endtask : reset_signals
Clocking block inputs are read-only; You cannot drive them.
Ether remove the driving statement, or change the clocking block direction of that signal to output ot inout.
I write ldpc_if.sv and ldpc_transaction.sv as follows.
"ldpc_if.sv"
interface ldpc_if#(parameter COLS=9216, parameter ROWS=1024) (input clk, input reset);
logic [COLS-ROWS-1:0] en_enq_data;
logic en_enq_valid;
logic en_enq_ready;
logic [ROWS-1:0] en_deq_data;
logic en_deq_valid;
logic en_deq_ready;
logic [COLS-1:0] de_enq_data;
logic de_enq_valid;
logic de_enq_ready;
logic [COLS-1:0] de_deq_data;
logic de_deq_valid;
logic de_deq_ready;
endinterface
"ldpc_transaction.sv"
class ldpc_transaction#(parameter WIDTH=8192) extends uvm_sequence_item;
rand bit [WIDTH-1:0] data;
bit [8191:0] encode_data_in;
bit [1023:0] encode_data_out;
bit [9215:0] decode_data;
`uvm_object_utils(ldpc_transaction)
function new(string name = "ldpc_transaction");
super.new();
endfunction
endclass
And I write ldpc_monitor.sv to monitor interface.
task ldpc_monitor::collect_one_pkt(ldpc_transaction tr);
while(1) begin
#(posedge vif.clk);
if(vif.en_enq_valid && vif.en_enq_ready) break;
end
tr.encode_data_in <= vif.en_enq_data;
while(1) begin
#(posedge vif.clk)
if(vif.en_deq_valid && vif.en_deq_ready) break;
end
tr.encode_data_out <= vif.en_deq_data;
while(1)begin
#(posedge vif.clk)
if(vif.de_deq_valid && vif.de_deq_ready)begin
break;
end
end
tr.decode_data <= vif.de_deq_data;
$display("tr.decode_data = %0h", tr.decode_data);
$display("vif.de_deq_data = %0h", vif.de_deq_data);
endtask
vcs compiles all files successfully. However, tr.decode_data is always displayed as zero. But, vif.de_deq_data is correct. Why is vif.de_deq_data not assigned to tr.decode_data.
It's because the $display you've used to display your transaction is blocking. Conversely, you've used an non-blocking assignment to set tr.decode_data.
Thus, your $display statement actually gets executed before your assignment. Getting a 0 is just an artefact of your simulator - could be any random stuff in the memory assigned to that variable (though most simulators just reset to 0).
Quick search revealed this useful example which illustrates exactly your problem.
https://verificationguide.com/systemverilog/systemverilog-nonblocking-assignment/
I am generating a divided clock, something like this:
logic div_clk;
always_ff #(posedge clk or negedge rstb) begin
if(!rstb) div_clk <= 1'b0;
else div_clk <= !div_clk;
end
I then launch data on clk and capture on div_clk. Something like this:
always_ff #(posedge clk) begin
clk_data <= something;
end
always_ff #(posedge div_clk) begin
div_clk_data <= clk_data;
end
In my simulations I am getting a race condition since clk_data updates coincident with div_clk and the div_clk_data gets the wrong value.
In synthesis I define these two clocks to be synchronous by creating a generated clock:
create_clock -name CLK [get_ports clk]
create_generated_clock -name GEN_DIV_CLK -source [get_ports clk] -divide_by 2 [get_pins div_clk]
Is there something equivalent that I can put into my RTL, or something I can do to tell my simulator that div_clk is synchronous to clk and prevent the race condition from happening?
This is a case where NBA's should not be used. You should not have any NBA's in your clock tree (including gated clocks) if you want the clocks to remain synchronous.
Is there any way to interrogate whether the simulation is at the #(posedge clk) event aside from using a named event that's triggered at the same time?
With the following code, I can make sure that I only do stuff at the posedge of a clock:
module tb;
bit clk;
always #2 clk = ~clk;
event pos_clk;
always #(posedge clk)
-> pos_clk;
initial begin
// stuff happens
#(posedge clk);
$display("[%0d] #(posedge clk)", $time());
// control is passed asynchronously to some task
// - since it's already at a posedge, it doesn't need to wait
some_task();
// other stuff happens
#1;
$display("[%0d] #1", $time());
// control is passed asynchronously to some task
// - since it's not at a posedge, it needs to catch the next one
some_task();
$finish();
end
task some_task();
wait (pos_clk.triggered);
$display("[%0d] wait (pos_clk.triggered)", $time());
// do relevant stuff
endtask
endmodule
Is there some other way I could do this without the extra named event?
This is what the ##0 construct does (See section 14.11 Cycle delay: ## of the 1800-2012 LRM). You do have to define a default clocking block, which means your task has to be defined inside a module or interface
module tb;
bit clk;
always #2 clk = ~clk;
default clocking cb #(posedge clk)
endclocking
initial begin
// stuff happens
#(cb) // when using clocking blocks, only use the clocking event
$display("[%0d] #(posedge clk)", $time());
// control is passed asynchronously to some task
// - since it's already at a posedge, it doesn't need to wait
some_task();
// other stuff happens
#1;
$display("[%0d] #1", $time());
// control is passed asynchronously to some task
// - since it's not at a posedge, it needs to catch the next one
some_task();
$finish();
end
task some_task();
##0;
$display("[%0d] wait (pos_clk.triggered)", $time());
// do relevant stuff
endtask
endmodule
My advice would be not to do either and figure out a way to keep the activation of some_task synchronous.
Let's say I have a bi-directional interface. I want the TB to be able to receive data from the DUT and I want the TB to be able to drive data to the DUT. I need to put in a clocking block in my code because I have race-condition issues. I can fix these issues by putting in a little #1 in the right spot, but I know that a clocking block is the correct solution. The part I'm having difficulty with is the bi-directional part. If it was one direction I might be OK, but the syntax for bi-directional interface is tripping me up. Is the right solution to make 2 clocking blocks, or 2 modports, or something else entirely?
interface MyInterface
(input bit i_Clk);
logic [15:0] r_Data;
logic r_DV = 1'b0;
clocking CB #(posedge i_Clk);
default input #1step output #1step;
endclocking : CB
task t_Clock_Cycles(int N);
repeat (N) #(posedge i_Clk);
endtask : t_Clock_Cycles
modport Driver (clocking CB, output r_Data, r_DV);
modport Receiver (clocking CB, input r_Data, r_DV);
endinterface : MyInterface
package MyPackage;
class MyDriver;
virtual MyInterface.Driver hook;
function new(virtual MyInterface.Driver hook);
this.hook = hook;
endfunction : new
task t_Drive(input [15:0] i_Data);
forever
begin
hook.CB.r_Data = i_Data;
hook.CB.r_DV = 1'b1;
hook.CB.t_Clock_Cycles(1);
end
endtask : t_Drive
endclass : MyDriver
endpackage : MyPackage
module MyModule;
import MyPackage::*;
logic r_Clk = 1'b0;
MyInterface hook(.i_Clk(r_Clk));
always #5 r_Clk = ~r_Clk;
MyDriver d1 = new(hook.Driver);
initial
begin
d1.t_Drive(16'hABCD);
end
endmodule // MyModule
The whole point of using a clocking block is to declare which signals you want to access synchronously. You should add your signals to the clocking block:
clocking CB #(posedge i_Clk);
default input #1step output #1step;
inout r_Data;
inout r_DV;
endclocking : CB
Since you also want to have different access permissions for your driver and receiver, this means you'll need two different clocking blocks:
clocking CB_driver #(posedge i_Clk);
default input #1step output #1step;
output r_Data;
output_DV;
endclocking : CB_driver
// ... direction reversed for CB_receiver
Unfortunately, it's not possible to say that you have a reference to a certain clocking block inside your driver/receiver classes:
class Driver
virtual MyInterface.CB_driver hook; // !!! Not allowed
endclass
If you want to restrict your driver to only be able to drive through CB_driver, you can use a modport:
interface MyInterface;
modport Driver(CB_driver);
endinterface
class Driver;
virtual MyInterface.Driver hook;
endclass
This way you can reference hook.CB_driver when driving your signals. The same goes for your receiver.