Is there a way to know in my testbench top about the current phase of the UVM hierarchy?. Since testbench top is a static module and UVM hierarchy is made of classes which are dynamic.
In my testbench top, I am directly driving few ports which is outside of UVM hierarchy. I need to stop driving these ports say after the shutdown phase. I can do it using uvm_config_db passing a phase from sequence but I don't want to create dependencies. I know it defeats the purpose of using UVM and reusability but just asking if I can do that?.
module top()
initial begin
drive_ports();
end
virtual task drive_ports()
//I need to keep driving these ports till shutdown_phase
if (!uvm_tb_hierarchy.phase == shutdown_phase) //?? How to get phase??
dut.port = 8'hff
dut.en = 1;
endtask
initial begin
run_test()
end
endmodule
You can try this to get the current phase.
uvm_root top;
uvm_phase curr_phase.
uvm_coreservice_t cs = uvm_coreservice_t::get();
top = cs.get_root();
curr_phase = top.m_current_phase;
Thanks, I tried the below code and it works. It seems each phase can be accessed at testbench top using "uvm_top.m_current_phase" provided you import uvm_pkg at testbench top. Since build_phase() starts at time 0, accessing this variable using initial_begin in testbench top was resulting in runtime error. So added wait statement in top TB and it works.
module top();
import uvm_pkg::*;
int shutdown;
initial begin
wait (uvm_top != null);
while (1) begin
#(uvm_top.m_current_phase);
if (uvm_top.m_current_phase != null) begin
case (uvm_top.m_current_phase.get_name())
"pre_shutdown": shutdown = 1;
endcase
end
end
end
endmodule
Related
I need to generate around 10,000 connectivity assertions to check that values driven at DUT interface at the beginning of simulation has reached (and is retained) at around 10,000 points inside the DUT throughout the simulation.
The 10k destination points inside DUT are available through xls, hence, if I can take the paths to an array, I could write a single assertion property and instantiate it multiple times while iterating through the array.
What is the better approach here for simulation performance?
Using assign :
logic[7:0] dest_vals[10000];
assign dest_vals[0] = dut_path0.sig0; //This assignment code can be script-generated
assign dest_vals[1] = dut_path1.sig1;
....
assign dest_vals[9999] = dut_path9999.sig9999;
property check_val(expected_val, dut_val);
#(posedge assert_clk) expected_val == dut_val;
endproperty
genvar i;
generate
for(i=0;i<9999;i++)
assert property check_val(exp_val[i], dest_vals[i]);
endgenerate
Using uvm_hdl_read :
string dest_val_path[10000] = '{
"dut_path0.sig0",
"dut_path1.sig1",
....
"dut_path9999.sig9999"
};
property check_val(expected_val, dut_val);
#(posedge assert_clk) expected_val == dut_val;
endproperty
genvar i;
generate
for(i=0;i<9999;i++) begin
initial forever begin
#(posedge assert_clk);
uvm_hdl_read(dest_val_path[i],dest_vals[i]);
end
assert property check_val(exp_val[i], dest_vals[i]);
end
endgenerate
Follow up question: Is there a way to change static array of size 10k to dynamic array/associative array/queue, so that if 10k destination points changes to 11k in future, array need not be re-sized manually?
Using uvm_hdl_read to access a signal by a string name is significantly slower than a direct hierarchical reference to a signal in an assign statement. A lot of code gets executed to lookup up that signal name in a string database and retrieve it from the simulator's internal database using the SystemVerilog's C based "VPI" routines. Plus, you can lose some optimizations because the value of the signal needs to be readily available at any point in time. In the case of the continuous assign statement, the simulator can work backwards and figure out it only needs the signal value on the assert_clk trigger.
How noticeable this performance difference is depends on a number of other factors
The overall size of the entire design's activity relative to additional code executed by uvm_hdl_read
How often the assert_clk triggers relative to the other activity in the design
How good a job you were able to limit VPI access to just the signals involved. Every signal you give VPI access to increases the size of the string database and prevents optimizations around that signal.
There is another option that does not involve assign statements or generate loops. You can use the bind construct to insert a module with your assertion. This works particularly well in your situation since you already have a script that produces the code for you.
module #(type T=logic [7:0]) mcheck(input logic clk, T expected_val, dut_val);
property check_val;
#(posedge clk) expected_val == dut_val;
endproperty
assert property(check_val);
endmodule
bind dut_path0 mcheck m(tb_path.assert_clk,tb_path.expected_val[0], sig0);
bind dut_path1 mcheck m(tb_path.assert_clk,tb_path.expected_val[1], sig1);
...
Note the port connections in the bind module are relative to the dut_path where mcheck is bound into.
I have a testbench in Vivado which has a hierarchy of IP--some custom IP and some Xilinx IP, like the Zynq Processing System. The Zynq Processing System also has an associated Verification IP library that has useful API for doing things like loading DDR.
I would like to write a task which leverages the Zynq Verification IP (and associated API) inside it. I can't figure out how I would implement this in my testbench? I am new to SV, and am guessing that I need to pass the zynq processing system object as an argument so I can access it's API inside my super-task.
Updated example of what I'm trying to do in my testbench. I realize this isn't proper SystemVerilog, it's just to demonstrate the functionality I'm trying to obtain. TOP is a module defined in some other .sv file that contains the definition of a task called T:
module tb();
TOP TIPTOP(), TIPITTYTOP();
task myTask(input TOP T);
begin
T.T;
end
endtask
initial begin
myTask(TIPTOP);
myTask(TIPITTYTOP);
end
endmodule
Another answer to the updated question
This can only be done if the module TOP is not a module but a different flavour of module, called an interface. There is a special kind of SystemVerilog variable called a virtual interface which is a variable that can store a reference to the instance of an interface. This is what you need here. So,
you need to make TOP an interface and
you need to add the keyword virtual to your task: task myTask(input virtual TOP T);
There are restrictions on an interface, however. (We are not quite using it for its normal purpose here.) The main one which might affect you is that you cannot instantiate a module inside an interface.
https://www.edaplayground.com/x/SM33
interface TOP;
task T;
$display("TOP.T");
endtask
endinterface
module tb();
TOP TIPTOP(), TIPITTYTOP();
task myTask(input virtual TOP T);
begin
T.T;
end
endtask
initial begin
myTask(TIPTOP);
myTask(TIPITTYTOP);
end
endmodule
You can call a task or function that is declared in another module. The code below has the following structure:
P
TOP ANOTHER_TOP
| |
BOT bot BOT bot
Package P and all modules have a task T declared in them. I can call all of the tasks from module TOP:
I can call the task in the package P using the score resolution operator, :::
P::T;
I can call the local task:
T;
I can call the task in the instance bot of BOT:
bot.T;
I can call the task in the other top-level module, ANOTHER_TOP:
ANOTHER_TOP.T;
I can call the task in the instance bot of BOT in the other top-level module:
ANOTHER_TOP.bot.T;
Notice how I have declared the various a tasks and modules "in the wrong order". This is OK, because Verilog takes 3 passes to compile and the relationships between the various tasks and modules are sorted out in passes 2 and 3. The package, however, has to be compiled first. This is because packages are a bit of an after-thought in the grand scheme of things.
https://www.edaplayground.com/x/KpJR
package P;
task T;
$display("P::T");
endtask
endpackage
module TOP;
initial
begin
T;
ANOTHER_TOP.T;
bot.T;
ANOTHER_TOP.bot.T;
P::T;
end
task T;
$display("TOP.T");
endtask
BOT bot ();
endmodule
module ANOTHER_TOP;
task T;
$display("ANOTHER_TOP.T");
endtask
BOT bot ();
endmodule
module BOT;
task T;
$display("BOT.T");
endtask
endmodule
I'm trying to write a memory scheduling testbench and to verify that I am accessing the correct addresses and writing the correct values at the right time I want to compare what is going on with the signals inside my top module with my schedule that I developed.
I've tried looking up "dot notation" and using my simulator (ModelSim) to access the signal (which I can do on the waveform fine) but I want to be able to use SVAs to check I have the correct values.
module top(input d, output q)
//wires
wire sub1_output
// Instantiate submodule
sub_module1 sub1(.sub1_output(sub1_output));
always begin
// logic
end
endmodule
module tb_top();
reg d;
wire q;
DUT top(.*);
initial begin
// This is where I want to access something within my DUT
assert(DUT.sub1_output == 1'b1)
end
endmodule
When I try this my code compiles and runs, but if I write the assertion such that it should fail and stop my code, nothing happens.
DUT.sub1_output
Is the correct format to use assertions on signals within top level instantiations.
I have written an UVM testbench that has 3 agents and am now in the process of writing a scoreboard/checker. I need to have a checker module for my SystemVerilog Assertions, but this checker module needs to be aware of register configuration that is done from the test (and can be random, decided during run_phase of the test).
I am unable to figure out how this would work? If I were to create a checker module for my assertions, and bind it at the top level (tb_top) to the dut, how does this checker module know my register configuration?
After reading some papers, I figured I could write my checker module as an interface, set it in tb_top. But this would give access to the variables in my interface to the UVCs. How does the interface access variables in the UVCs?
Any help is appreciated. I feel I am missing something key here as this has probably been done plenty of times before.
EDIT: Please don't tell me I have to implement some kind of API to set each individual register setting from my UVCs? I want to just get a handle to my reg_block (or any other config variable in my agents)
It seems that you want to pass information from tb_top to your UVC or vice versa. This information will be used by your assertion in tb_top, and shared by your UVC. My suggestion, you can either use uvm_resource_db or uvm_config_db.
I can think of two ways of achieving this communication.
First method is set the configuration in your tb_top, then your UVC grab this handle. From here on, you can communicate your register or whatever info you need for your assertion.
class my_tb_config extends uvm_object;
// ...
endclass
module tb_top;
my_tb_config tcfg;
initial begin
tcfg = new("tcfg");
uvm_config_db#(my_tb_config)::set(uvm_root::get(), "*", "my_tb_config", tcfg);
end
endmodule
// somewhere in your UVC
class my_uvc extends uvm_component;
my_tb_config tcfg;
function void build_phase(uvm_phase phase);
// now both tb_top and your UVC point to the same config object
void'(uvm_config_db#(my_tb_config)::get(this,"","my_tb_config", tcfg));
endfunction
endclass
Another method is the other way around. Pass your UVC configuration to your tb_top.
class my_other_uvc extends uvm_component;
my_tb_config tcfg;
function void build_phase(uvm_phase);
tcfg = new("tcfg");
uvm_resource_db#(my_tb_config)::set("*", "my_tb_config", tcfg);
endfunction
endclass
// somewhere in your tb_top
module tb_top;
my_tb_config tcfg;
initial begin
#1ps; // small delay, making sure resource is submitted
void'(uvm_resource_db#(my_tb_config)::read_by_name("*","my_tb_config",tcfg);
// Now both your tb_top and UVC share same object, so you can freely define your whatever communication between them
end
endmodule
I figured out a way to do this. Firstly, I realized that I had asked two separate questions:
1) My checker module needs to be aware of register configuration that is done from the test
I use cross module reference into my design to access my registers, and this provides me with up-to date register configuration as set by the test during the run-phase.
tb.sv
module tb;
dut my_dut( ... )
interface my_checker (
.input_registerA (tb.my_dut.my_sub_module.regA),
.input_registerB (tb.my_dut.my_sub_module.regB),
.input_registerC (tb.my_dut.my_other_sub_module.regC),
....
)
endmodule
my_checker.sv
interface my_checker (
input input_registerA,
input input_registerB,
input input_registerC,
....
);
// Here I can write properties/assertions that are register-aware
endinterface
2) How does the interface access variables in the UVCs?
This is a little trickier. I want to dynamically update my checker variables from the uvm_sequence or uvm_monitor etc.
I read this paper by Verilab that clearly describes the method to do this:
http://www.verilab.com/files/litterick_sva_encapsulation.pdf
In my checker module, I create a uvm_component. From this component, I now have access to the uvm_resource_db, through which I can exchange info with my UVM-testbench.
One thing to remember is that the uvm_component instantiated in the checker module is located at the top-level (uvm_root).
I want to write some tasks in a package, and then import that package in some files that use those tasks.
One of these tasks toggles a reset signal. The task is reset_board and the code is as follows:
package tb_pkg;
task reset_board(output logic rst);
rst <= 1'b0;
#1;
rst <= 1'b1;
#1;
rst <= 1'b0;
#1;
endtask
endpackage
However, if I understand this correctly, outputs are only assigned at the end of execution, so in this case, the rst signal will just get set to 0 at the end of the task's execution, which is obviously not what I want.
If this task were declared locally in the module in which it is used, I could refer to the rst signal directly (since it is declared in the module). However, this would not allow me to put the task in a separate package. I could put the task in a file and then `include it in the module, but I'm trying to avoid the nasty complications that come with the way SystemVerilog handles includes (long-story-short, it doesn't work the way C does).
So, is there any way that the task can drive an output with different values across the duration of its execution without it having to refer to a global variable?
A quick solution is to use a ref that passes the task argument by reference instead of an output argument that is copied after returning from the task.
task reset_board(ref logic rst);
There are a few drawbacks of doing it this way. You can only pass variables of matching types by reference, so when you call reset_board(*signal*), signal cannot be a wire. Another problem is you cannot use an NBA <= to assign a variable passed by reference, you must use a blocking assignment =. This is because you are allowed to pass automatic variables by reference to a task, but automatic variable are not allowed to be assigned by NBAs. There is no way for the task to check the storage type of the argument passed to it.
Standard methodologies like the UVM recommend using virtual interfaces or abstract classes to create these kinds of connections from the testbench to the DUT. See my DVCon paper for more information.