Error "Makefrag-verilator:20: recipe for target" while running "make" in VCS, Emulator Vsim directories - rocket-chip

Question

I am working on building the Rocket-Chip on my Ubuntu 18.04. I have already built the RISC-V toolchain, RISC-V Tools, Rocket-Tools, Vertilator, Sbt on my machine.
I am following the guidelines demonstrated on https://github.com/chipsalliance/rocket-chip
So, I followed the following steps:
Changed directory to rocket-chip/emulator
run make
Then, every time, I face the same error below (Head to the last line of the running log), given that I face exactly the same error whenever I try to build the VCS, or run the make verilog in Vsim directory.
How can I solve this issue, given that I reinstalled the vertilator as explained in Chisel3 respo on Github.
find: ‘/home/user/rocket-chip/api-config-sifive/design/craft/src/main/scala’: No such file or directory
mkdir -p /home/user/rocket-chip/emulator/generated-src/
cd /home/user/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar /home/user/rocket-chip/sbt-launch.jar "runMain freechips.rocketchip.system.Generator /home/user/rocket-chip/emulator/generated-src freechips.rocketchip.system TestHarness freechips.rocketchip.system DefaultConfig"
OpenJDK 64-Bit Server VM warning: Ignoring option MaxPermSize; support was removed in 8.0
[info] Loading settings for project rocket-chip-build from plugins.sbt ...
[info] Loading project definition from /home/user/rocket-chip/project
[info] Loading settings for project rocketchip from build.sbt ...
[info] Loading settings for project hardfloat from build.sbt ...
[info] Loading settings for project api-config-chipsalliance from build.sbt ...
[info] Loading settings for project chisel from build.sbt ...
Using addons:
[info] Set current project to rocketchip (in build file:/home/user/rocket-chip/)
[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list
[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list
[info] Running freechips.rocketchip.system.Generator /home/user/rocket-chip/emulator/generated-src freechips.rocketchip.system TestHarness freechips.rocketchip.system DefaultConfig
[info] [0.005] Elaborating design...
Interrupt map (2 harts 2 interrupts):
[1, 2] => dut
<stdout>: Warning (simple_bus_reg): Node /soc/external-interrupts missing or empty reg/ranges property
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-unknown";
L13: cpus {
#address-cells = <1>;
#size-cells = <0>;
L6: cpu#0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
hardware-exec-breakpoint-count = <1>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L8>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L4: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L8: memory#80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
L12: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
L2: clint#2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L3: debug-controller#0 {
compatible = "sifive,debug-013", "riscv,debug-013";
debug-attach = "dmi";
interrupts-extended = <&L4 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L0: error-device#3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
};
L7: external-interrupts {
interrupt-parent = <&L1>;
interrupts = <1 2>;
};
L1: interrupt-controller#c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L4 11 &L4 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <3>;
riscv,ndev = <2>;
};
L9: mmio-port-axi4#60000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x60000000 0x20000000>;
};
L10: rom#10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x10000>;
reg-names = "mem";
};
};
};
Generated Address Map
0 - 1000 ARWX debug-controller#0
3000 - 4000 ARWX error-device#3000
10000 - 20000 R X rom#10000
2000000 - 2010000 ARW clint#2000000
c000000 - 10000000 ARW interrupt-controller#c000000
60000000 - 80000000 RWX mmio-port-axi4#60000000
80000000 - 90000000 RWXC memory#80000000
[deprecated] Data.scala:486 (10378 calls): litArg is deprecated: "litArg is deprecated, use litOption or litTo*Option"
[warn] There were 1 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn] In the sbt interactive console, enter:
[warn] set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn] or, in your build.sbt, add the line:
[warn] scalacOptions := Seq("-unchecked", "-deprecation")
[info] [15.855] Done elaborating.
[success] Total time: 21 s, completed Nov 7, 2019, 3:31:59 PM
mkdir -p /home/user/rocket-chip/emulator/generated-src/
java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp "/home/user/rocket-chip/firrtl/utils/bin/firrtl.jar":""/home/user/rocket-chip/target/scala-2.12/classes:/home/user/rocket-chip/chisel3/target/scala-2.12/*"" firrtl.Driver -i /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.fir -o /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.v -X verilog --infer-rw TestHarness --repl-seq-mem -c:TestHarness:-o:/home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.conf -faf /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.anno.json -td /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig/
OpenJDK 64-Bit Server VM warning: Ignoring option MaxPermSize; support was removed in 8.0
------------------------------------------------------------------------------
Warning: firrtl.Driver is deprecated since 1.2!
Please switch to firrtl.stage.FirrtlMain
------------------------------------------------------------------------------
Total FIRRTL Compile Time: 60111.0 ms
cd /home/user/rocket-chip/emulator/generated-src && \
/home/user/rocket-chip/scripts/vlsi_mem_gen /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.conf > /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v.tmp && \
mv -f /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v.tmp /home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v
/usr/bin/env: ‘python’: No such file or directory
Makefrag-verilator:20: recipe for target '/home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v' failed
make: *** [/home/user/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v] Error 127

Answer 1

It says that it cannot find Python on the path. It might stem from line-ending convention. Please try to convert the script to Unix line-ending.