I am using STM32H7 family of microcontroller as SPI Master Transmit device which needs to talk to 4 SPI slave devices receive only which are also all STM32H7 MCU's. Both master and slave are configured for software slave management.
The confusion is how slave will identify when master wants to talk to it or transmit data to it without using hardware NSS pin?
How slave device will start receiving in this scenario and stop receiving when all data transmitted?
If you use software slave select (NSS), you must select and deselect the SPI interface by software.
Typically, you would setup an external interrupt on the pin used as NSS/CS and select/deselect the SPI interface when the interrupt is triggered.
On an STM32F1 chip, the SPI interface is selected/deselected by setting/clearing the SSI bit in the SPI_CR1 register. I assume it's very similar on a STM32H7 chip.
Update
I've just checked the STM32H7 and it's exactly the same.
It is very simple. Every slave has one pin called CS. You need to select this device by setting this pin just by using the GPIO. Then you can transmit or receive data. Remember that master has to supply clock even if it wants only to receive data.
It seems that the code shown below can manage the problem.
__HAL_SPI_ENABLE(&hspi1);
__HAL_SPI_DISABLE(&hspi1);
Related
Can a device connected to main processor can initiate a i2c communication.
For example, FAN connected using i2c bus, is it possible for a FAN to send a feedback to main processor.
Common solution to a problem like this is to have a separate interrupt line.
I3C supports in-band interrupts, if you're not set on I2C yet.
Please clarify above question that i was being asked in interview in one company.
And How slave device will communicate to master if at the same time slave device receives request from two or multiple master?
If we have I2C device (Master and Slave connected then how the speed of the data transfer between master and slave will be decided weather to use 100kbps normal mode or 400kbps fast mode)?
The i2c slave devices (from a small sensor to cameras in mobile (in cmos cameras, for control interface, not data is i2c interface)) comes with the supported i2c clock rates mentioned in the datasheet. Similarly, the master devices also come with the i2c max. supported clock rates. The speed of slower(from master and slave) will be speed of the i2c communication.
If you are trying to detect the frequency at runtime (i.e. not knowing the supported rate of slave device) is not recommended for embedded devices. (since they are not hot-plug in the most cases).
So, for example the i2c rate is configured 400kHz for master and slave is supporting till 100kHz, then it will be problem. Master needs to configure <= 100kHz.
If slave supports till 400kHz and master is configured 100kHz (though it is capable of supporting 400kHz), then there is no problem. In this case, the speed is decided according to your speed requirements. If you need more speed (4x speed), then configure the master at 400kHz, and if you are satisfied with the performance at 100kHz, then configure to 100kHz for power saving. You can also configure the master at custom frequency between 100kHz and 400kHz in this case.
If multiple devices with different i2c rates are interfaced on same bus, then the lowest should be the speed. Since it is difficult to change the i2c clock rate runtime in most cases. (e.g. In linux kernel the clock rate and its settings are provided by device tree.)
For multiple master and one slave communication, read this
The Arm processor on one of our boards has an spi port with two chip select lines.
It is mentioned in the processor's datasheet that it can control upto two spi devices.
Is it possible to use a GPIO as a slave select for an additional spi device?
How to modify the existing libraries/device drivers to support this change?
So far i've found a file in the kernel's source which contains the addresses of SPI port pins. Can anyone plz tell in which direction should i proceed?
If you have enough pins, you can bitbang the whole SPI protocol and use as many CS as you need.
You don't mention what processor it is. You have three possibilities.
If the processor has an i/o mux capabilities, turn off the SPI chip select functionality. The SPI controller will think it has asserted the line, but it won't go external.
Don't connect one SPI chip select. Use a pull-up/down for ESD protection.
Multiplex the chip select as per Joachim Isaksson
In first two cases, connect GPIOs to the additional device's chip select. Toggle the GPIO manually before running spi_write(), etc. This will allow the SPI controller to transfer at higher rates than are possible with bit banging and is a better system design. Ie, lower power consumption, lower CPU use, faster data rates, etc. If the peripheral is just for setup/boot, then the bit banging makes sense for simplicity. However, if your main operation depends on the SPI bus, you could consider this solution.
If only one peripheral needs the SPI for setup AND you have the i/o mux, you can disable the chip select functionality during setup, using a GPIO to select the setup peripheral and then re-enable the spi chip select during standard system operation for the other peripheral.
Using a GPIO doesn't require user space intervention. Drivers can provide call backs to set the GPIO when in use, so SPI commands can be buffered/queued and these solutions still work. For instance, the IMX SPI driver supports GPIO toggle by passing a negative chip select number to denote a GPIO id.
Note: Some SPI devices may require the chip select to toggle between words; what ever a word is for the device. Some controller may leave the chip select asserted when transferring multiple words. You need to get this right if you use a GPIO to manually select devices. I am sure some standard defines this, but definitely some device don't follow the standard.
Addendum: Most drivers support a GPIO chip select; via a negative chip select value. They will call Linux GPIO functions. Write a GPIO handler that does the de-multiplexing. No need to alter the SPI drivers.
The Arm processor on one of our boards has an spi port with two chip select lines.
It is mentioned in the processor's datasheet that it can control upto two spi devices.
Is it possible to use a GPIO as a slave select for an additional spi device?
How to modify the existing libraries/device drivers to support this change?
So far i've found a file in the kernel's source which contains the addresses of SPI port pins. Can anyone plz tell in which direction should i proceed?
If you have enough pins, you can bitbang the whole SPI protocol and use as many CS as you need.
You don't mention what processor it is. You have three possibilities.
If the processor has an i/o mux capabilities, turn off the SPI chip select functionality. The SPI controller will think it has asserted the line, but it won't go external.
Don't connect one SPI chip select. Use a pull-up/down for ESD protection.
Multiplex the chip select as per Joachim Isaksson
In first two cases, connect GPIOs to the additional device's chip select. Toggle the GPIO manually before running spi_write(), etc. This will allow the SPI controller to transfer at higher rates than are possible with bit banging and is a better system design. Ie, lower power consumption, lower CPU use, faster data rates, etc. If the peripheral is just for setup/boot, then the bit banging makes sense for simplicity. However, if your main operation depends on the SPI bus, you could consider this solution.
If only one peripheral needs the SPI for setup AND you have the i/o mux, you can disable the chip select functionality during setup, using a GPIO to select the setup peripheral and then re-enable the spi chip select during standard system operation for the other peripheral.
Using a GPIO doesn't require user space intervention. Drivers can provide call backs to set the GPIO when in use, so SPI commands can be buffered/queued and these solutions still work. For instance, the IMX SPI driver supports GPIO toggle by passing a negative chip select number to denote a GPIO id.
Note: Some SPI devices may require the chip select to toggle between words; what ever a word is for the device. Some controller may leave the chip select asserted when transferring multiple words. You need to get this right if you use a GPIO to manually select devices. I am sure some standard defines this, but definitely some device don't follow the standard.
Addendum: Most drivers support a GPIO chip select; via a negative chip select value. They will call Linux GPIO functions. Write a GPIO handler that does the de-multiplexing. No need to alter the SPI drivers.
Is there a sample i2c master code that supports rtc s35390a hardware clock? I am currently working on an SOC that needs to support s35390a from Seiko. But currently, i am getting an error rtc-s35390a 0-0030: hctosys: unable to read the hardware clock. I cannot read/write data properly. I am implementing combined form of transmission.
Use oscilloscope to check if I2C SCL/SDA show some thing
If you can get the first address correct waveform, You will easy to get the register value
This might not be a rtc chip problem.