I keep getting an error that says:
line 25: type error near num_values ; current type unsigned; expected
type unsigned.
It is already the type that is supposed to be, and I think it is same in bit length and declared alright, what am I doing wrong here?
The code is about implementation of fifo queue structure.
<Queue.vhd>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Queue is
port (
-- clock
clk: in std_logic;
-- input
push: in std_logic;
push_data: in std_logic_vector(31 downto 0);
pop: in std_logic;
-- output
pop_data: out std_logic_vector(31 downto 0);
num_values: out unsigned(31 downto 0)
);
end entity;
architecture Behavioral of Queue is
type items is array(0 to 31) of std_logic_vector(31 downto 0);
signal manager : items := (others => (others => '0'));
signal push_idx, pop_idx : integer := 0;
begin
process(clk) is
variable howmany : integer := 0;
begin
if rising_edge(clk) then
if (push = '1') then
manager(push_idx) <= push_data;
push_idx <= push_idx + 1;
howmany := howmany + 1;
end if;
if (pop = '1') then
if (howmany /= 0) then
pop_data <= manager(pop_idx);
pop_idx <= pop_idx + 1;
howmany := howmany - 1;
end if;
else
pop_data <= std_logic_vector(to_unsigned(0,pop_data'length));
end if;
if (push_idx = 31) then
push_idx <= 0;
end if;
if (pop_idx = 31) then
pop_idx <= 0;
end if;
num_values <= to_unsigned(howmany,32);
end if;
end process;
end architecture;
<QueueTb.vhd>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity QueueTb is
end entity;
architecture sim of QueueTb is
constant ClockFrequency : integer := 100e6;
constant ClockPeriod : time := 1000ms / ClockFrequency;
signal clk : std_logic := '0';
signal push, pop : std_logic := '0';
signal num_values : unsigned(31 downto 0);
signal push_data, pop_data : std_logic_vector(31 downto 0) := (others =>'0');
begin
UUT : entity work.Queue(Behavioral)
port map(
clk => clk,
push => push,
pop => pop,
num_values => num_values, <=== this is where error occurs!
push_data => push_data,
pop_data => pop_data);
clk <= not clk after ClockPeriod / 2;
process is
begin
wait for 10 ns;
push <= '1';
push_data <= conv_std_logic_vector(123,32);
wait for 10 ns;
push_data <= conv_std_logic_vector(456,32);
wait for 10 ns;
push <= '0';
push_data <= conv_std_logic_vector(0,32);
pop <= '1';
wait for 10 ns;
pop <= '0';
push <= '1';
push_data <= conv_std_logic_vector(789,32);
wait for 10 ns;
push <= '0';
pop <= '1';
wait for 80 ns;
end process;
end architecture;
What am I doing wrong here??
In the Queue entity you are using ieee.numeric_std and in the QueueTB you are using ieee.std_logic_arith . Both define different unsigned types.
Delete std_logic_arith from the testbench as it is not a standard VHDL library and use numeric_std instead.
Related
I'm trying to implement a circuit for a digital signature (RSA) on a FPGA Digilent Basys.
I ended to write down all the components and the top level entity. The Control Unit is formed by a Finit State Machine that controls the whole circuit.
But when I load it on my Basys, it seems to freeze in the State "V_wait_sign".
I can say that because how you can see in the FSM, in the state "V_wait_sign" I puts Leds out to "00100", so just the Led2 is On.
Below the code of the Top Level Entity and the FSM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FirmaDigitale is
Port ( Clock : in STD_LOGIC;
Buttons : in STD_LOGIC_VECTOR (3 downto 0);
Switches : in STD_LOGIC_VECTOR (7 downto 0);
Leds : out STD_LOGIC_VECTOR (7 downto 0);
Cathodes : out STD_LOGIC_VECTOR (7 downto 0);
Anodes : out STD_LOGIC_VECTOR (3 downto 0));
end FirmaDigitale;
architecture Structural of FirmaDigitale is
component Comparator32
Generic(width : Positive := 32);
Port ( a : in STD_LOGIC_VECTOR (width-1 downto 0);
b : in STD_LOGIC_VECTOR (width-1 downto 0);
Clock : in STD_LOGIC;
Comp_en : in STD_LOGIC; -- 1 attivo
equal : out STD_LOGIC;
Notequal : out STD_LOGIC);
end component;
component Decoder_2_4
Port ( i : in STD_LOGIC_VECTOR (1 downto 0);
o : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component Decoder_Seven_segm
Port ( Ing : in STD_LOGIC_VECTOR (3 downto 0);
Cathodes : out STD_LOGIC_VECTOR (6 downto 0));
end component;
component FSM_RSA
Port (
Clock : in STD_LOGIC; -- Clock
--in
Start_sign : in STD_LOGIC; --start sign
Load : in STD_LOGIC; --load 8 bits
Verify : in STD_LOGIC; --start verify signature
Done : in STD_LOGIC; --end message
Exp_Done : in STD_LOGIC; --end exp operation
Count_hit :in STD_LOGIC; --signature load
Count_eq :in STD_LOGIC; --
Count_neq :in STD_LOGIC; --
--control
Enable_Hash : out STD_LOGIC; -- Enable hash '0' attivo (2colpi)
Enable_Exp : out STD_LOGIC; -- Enable exp '1' attivo
Enable_RegExp : out STD_LOGIC; -- Enable RegExp '0' attivo
Enable_sign_reg : out STD_LOGIC; -- Enable sign_reg '0' attivo
Enable_comp : out STD_LOGIC; -- Enable Comparator '1' attivo
Enable_Disp : out STD_LOGIC_VECTOR(3 downto 0); -- Enable 7segm '0' attivo
Leds_step : out STD_LOGIC_VECTOR(4 downto 0);
Mux_sel : out STD_LOGIC; -- 1 per verifica, 0 per firma
Mux_disp : out STD_LOGIC; -- 1 MSB, 0 LSB
Reset_State : out STD_LOGIC -- Reset '0' attivo
);
end component;
component HashFunction
Generic( width : integer := 32; width_reg : integer := 8);
Port ( CharacterByte : in STD_LOGIC_VECTOR(width_reg-1 downto 0);
Clock : in STD_LOGIC;
Reset : in STD_LOGIC; --0 attivo
Reg_en : in STD_LOGIC; --0 attivo
Digest : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end component;
component Mux_2n_1n
Generic(width : integer := 8);
Port ( a : in STD_LOGIC_VECTOR(width-1 downto 0);
b : in STD_LOGIC_VECTOR(width-1 downto 0);
s : in STD_LOGIC;
o : out STD_LOGIC_VECTOR(width-1 downto 0));
end component;
component RAsync_2UpNCount_UpCounter
Generic (width : integer := 2);
Port ( clock : in STD_LOGIC; -- Clock
reset : in STD_LOGIC; -- Segnale di reset 0 attivo
en : in STD_LOGIC; -- Segnale di enable 1 attivo
count : out STD_LOGIC_VECTOR (width-1 downto 0) := (others => '0')); -- conteggio attuale
end component;
component SignReg
Generic( width : integer := 32; width_reg : integer := 8 );
Port ( SignatureByte : in STD_LOGIC_VECTOR (width_reg-1 downto 0);
Reset : in STD_LOGIC;
Count_En : in STD_LOGIC;
Clock : in STD_LOGIC;
hit : out STD_LOGIC;
Signature : out STD_LOGIC_VECTOR (width-1 downto 0));
end component;
component exponentiator
Generic (n : integer := 32);
Port (
x, y, m: in std_logic_vector(n-1 downto 0);
z: inout std_logic_vector(n-1 downto 0);
clk, reset, start: in std_logic;
done: out std_logic
);
end component;
component display_7_segments
Generic(
clock_frequency_in : integer := 50000000;
clock_frequency_out : integer := 50000000
);
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
digits : in STD_LOGIC_VECTOR (15 downto 0);
enable : in STD_LOGIC_VECTOR (3 downto 0);
dots : in STD_LOGIC_VECTOR (3 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
cathodes : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component Debouncer_xilinx is
Port ( CLK : in STD_LOGIC;
Sig : in STD_LOGIC;
Deb_Sig : out STD_LOGIC);
end component;
signal temp_exp_done, temp_enable_exp, sel_muxTo_display, temp_count_hit, temp_sel_EncDec, temp_comp_en, temp_eq, temp_not_eq, temp_en_RegExp : STD_LOGIC := '0';
signal temp_reset_state, temp_enable_hash, temp_en_SignReg : STD_LOGIC := '1';
signal temp_digest, temp_exp_out, temp_key, temp_sign, Exp_mux_out, RegExp_out : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal temp_enable_disp : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal temp_digits, temp_digits_to_display, temp_fin_digits : STD_LOGIC_VECTOR(15 downto 0);
signal Start_temp, Load_temp, Verify_temp, Done_temp : STD_LOGIC;
begin
deb_0: Debouncer_xilinx
port map(
CLK => Clock,
Sig => Buttons(0),
Deb_Sig => Start_temp
);
deb_1: Debouncer_xilinx
port map(
CLK => Clock,
Sig => Buttons(1),
Deb_Sig => Load_temp
);
deb_2: Debouncer_xilinx
port map(
CLK => Clock,
Sig => Buttons(2),
Deb_Sig => Verify_temp
);
deb_3: Debouncer_xilinx
port map(
CLK => Clock,
Sig => Buttons(3),
Deb_Sig => Done_temp
);
FSM: FSM_RSA
Port map (
Clock => Clock,
Start_sign => Start_temp,
Load => Load_temp, --load 8 bits
Verify => Verify_temp,
Done => Done_temp,
Exp_Done => temp_exp_done,
Count_hit => temp_count_hit,
Count_eq => temp_eq,
Count_neq => temp_not_eq,
--control
Enable_Hash => temp_enable_hash,
Enable_Exp => temp_enable_exp,
Enable_RegExp => temp_en_RegExp,
Enable_sign_reg => temp_en_SignReg,
Enable_comp => temp_comp_en,
Enable_Disp => temp_enable_disp,
Leds_step => Leds(4 downto 0),
Mux_sel => temp_sel_EncDec,
Mux_disp => sel_muxTo_display,
Reset_State => temp_reset_state
);
RegExp : entity work.Generic_RAsync_Register
generic map (width => 32)
port map (
D=> temp_exp_out,
clock => Clock,
reset => temp_reset_state,
en => temp_en_RegExp,
Q => RegExp_out
);
EncriptDecript: exponentiator
Generic map(n => 32)
Port map( x => temp_key,
y => Exp_mux_out,
m => x"0000008F", --143, p=11, q=13; pq=143
z => temp_exp_out,
clk => Clock,
reset => not temp_reset_state,
start => temp_enable_exp,
done => temp_exp_done
);
Leds(7) <= temp_exp_done;
Mux_Enc_Dec: Mux_2n_1n
Generic map(width => 32)
Port map( a => x"00000071", --113, Chiave Privata
b => x"00000011", --17, Chiave Pubblica
s => temp_sel_EncDec,
o => temp_key
);
RegistroFirma: SignReg
Generic map( width => 32, width_reg => 8 )
Port map( SignatureByte => Switches,
Reset => temp_reset_state,
Count_En => temp_en_SignReg,
Clock => Clock,
hit => temp_count_hit,
Signature => temp_sign
);
Exp_mux : Mux_2n_1n generic map (width => 32)
port map(
a => temp_digest,
b => temp_sign,
s => temp_sel_EncDec,
o => Exp_mux_out
);
HASH: HashFunction
Generic map( width => 32, width_reg => 8)
Port map( CharacterByte => Switches,
Clock => Clock,
Reset => temp_reset_state,
Reg_en => temp_enable_hash,
Digest => temp_digest
);
Display: display_7_segments
Generic map( clock_frequency_in => 50000000, clock_frequency_out => 1000 )
Port map( clock => Clock,
reset_n => temp_reset_state,
digits => temp_digits,
enable => temp_enable_disp,
dots => "0000",
anodes => Anodes,
cathodes => Cathodes
);
Mux_MSB_LSB: Mux_2n_1n
Generic map(width => 16)
Port map( a => RegExp_out(15 downto 0),
b => RegExp_out(31 downto 16),
s => sel_muxTo_display,
o => temp_digits
);
Compare: Comparator32
Generic map( width => 32 )
Port map( a => RegExp_out,
b => temp_sign,
Clock => Clock,
Comp_en => temp_comp_en,
equal => temp_eq,
Notequal => temp_not_eq
);
Leds(6) <= temp_eq;
Leds(5) <= temp_not_eq;
end Structural;
this is the FSM instead:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM_RSA is
Port (
Clock : in STD_LOGIC; -- Clock
--in
Start_sign : in STD_LOGIC; --start sign
Load : in STD_LOGIC; --load 8 bits
Verify : in STD_LOGIC; --start verify signature
Done : in STD_LOGIC; --end message
Exp_Done : in STD_LOGIC; --end exp operation
Count_hit :in STD_LOGIC; --signature load
Count_eq :in STD_LOGIC; --
Count_neq :in STD_LOGIC; --
--control
Enable_Hash : out STD_LOGIC; -- Enable hash '0' attivo (2colpi)
Enable_Exp : out STD_LOGIC; -- Enable exp '1' attivo
Enable_RegExp : out STD_LOGIC; -- Enable RegExp '0' attivo
Enable_sign_reg : out STD_LOGIC; -- Enable sign_reg '0' attivo
Enable_comp : out STD_LOGIC; -- Enable Comparator '1' attivo
Enable_Disp : out STD_LOGIC_VECTOR(3 downto 0); -- Enable 7segm '0' attivo
Leds_step : out STD_LOGIC_VECTOR(4 downto 0);
Mux_sel : out STD_LOGIC; -- 1 per verifica, 0 per firma
Mux_disp : out STD_LOGIC; -- 1 MSB, 0 LSB
Reset_State : out STD_LOGIC -- Reset '0' attivo
);
end FSM_RSA;
architecture Behavioral of FSM_RSA is
-- Definizione dell'insieme degli stati
type State is (Idle, V_wait8, S_wait8, V_Hash,V_waitReg, V_waitH, S_waitH, S_Hash, V_wait_sign, V_decrypt, V_comp, V_reg, S_encrypt, S_dispMSB, S_dispLSB);
-- Definizione dei segnali di "stato" e inizializzazione allo stato iniziale idle
signal Current_State, Next_State : State := Idle;
begin
-- Process per la gestione dell'evoluzione dello stato
state_management : process(Clock)
begin
if falling_edge(Clock) then
Current_State <= Next_State;
else
Current_State <= Current_State;
end if;
end process;
-- Process per la gestione della FSM
FSM : process(Current_State, Start_sign, Load, Verify, Done, Exp_Done, Count_eq, Count_neq, Count_hit)
begin
case Current_State is
--macchina in attesa di comandi. Tutti i registri disabilitati
when Idle =>
Enable_Hash <= '1';
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '0';
Mux_sel <= '0';
Mux_disp <= '0';
Leds_step <= "00000";
if (Verify = '1') then
Next_State <= V_wait8;
else
if ( Start_sign ='1') then
Next_state <= S_wait8;
else
Next_state <= Idle;
end if;
end if;
when S_encrypt =>
Enable_Hash <= '1';
Enable_Exp <= '1'; -- abilito
Enable_RegExp <= '0'; -- abilito
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0'; --decript M_h**d modn
Mux_disp <= '0';
Leds_step <= "00010";
if (Exp_Done = '1') then
Next_State <= S_dispMSB;
else
Next_state <= S_encrypt;
end if;
when S_dispLSB =>
Enable_Hash <= '1';
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "1111"; -- abilito
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '0'; --LSB
if (Done = '1') then
Next_State <= Idle;
else
Next_state <=S_dispLSB;
end if;
when S_dispMSB =>
Enable_Hash <= '1';
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "1111"; -- abilito
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '1'; --MSB
if (Load = '1') then
Next_State <= S_dispLSB;
else
Next_state <=S_dispMSB;
end if;
when S_waitH =>
Enable_Hash <= '1'; --disabilito tutto
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
if( Load = '0') then
Next_State <= S_wait8;
else
Next_State <= S_waitH;
end if;
when S_Hash =>
Enable_Hash <= '0'; -- abilito
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '0';
Next_State <= S_waitH;
when S_wait8 =>
Enable_Hash <= '1'; --disabilito tutto
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '0';
Leds_step <= "00001";
if (Done = '1') then
Next_State <= S_encrypt;
else
if ( Load = '1') then
Next_state <= S_Hash;
else
Next_state <= S_wait8;
end if;
end if;
when V_comp =>
Enable_Hash <= '1';
Enable_Exp <= '0';
Enable_RegExp <= '0';
Enable_sign_reg <= '1';
Enable_comp <= '1'; -- abilito
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '1'; --decript M_h**e modn
Mux_disp <= '0';
Leds_step <= "10000";
if (Count_eq = '1' OR Count_neq ='1') then
if (Done = '1') then
Next_State <= Idle;
end if;
end if;
when V_decrypt =>
Enable_Hash <= '1';
Enable_Exp <= '1'; -- abilito
Enable_RegExp <= '0'; -- abilito
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '1'; --decript M_h**e modn
Mux_disp <= '0';
Leds_step <= "01000";
if (Exp_Done = '1') then
Next_State <= V_comp;
else
Next_state <= V_decrypt;
end if;
when V_Reg =>
Enable_Hash <= '1';
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '0'; -- abilito
Enable_comp <= '0';
Enable_Disp <= "1111";
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '0';
if( Count_hit = '1') then
Next_State <= V_decrypt;
else
Next_State <= V_waitReg;
end if;
when V_waitReg =>
Enable_Hash <= '1'; --disabilito tutto
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '0';
if( Load = '0') then
Next_State <= V_wait_sign;
else
Next_State <= V_waitReg;
end if;
when V_wait8 =>
Enable_Hash <= '1'; --disabilito tutto
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '0';
if (Done = '1') then
Next_State <= V_wait_sign;
else
if ( Load = '1') then
Next_state <= V_Hash;
else
Next_state <= V_wait8;
end if;
end if;
when V_Hash =>
Enable_Hash <= '0'; -- abilito
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
Mux_disp <= '0';
Next_State <= V_waitH;
when V_waitH =>
Enable_Hash <= '1'; --disabilito tutto
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
if( Load = '0') then
Next_State <= V_wait8;
else
Next_State <= V_waitH;
end if;
when V_wait_sign =>
Enable_Hash <= '1'; --disabilito tutto
Enable_Exp <= '0';
Enable_RegExp <= '1';
Enable_sign_reg <= '1';
Enable_comp <= '0';
Enable_Disp <= "0000";
Reset_State <= '1';
Mux_sel <= '0';
Leds_step <= "00100";
if (Load = '1') then -- AND Count_hit = '0') then
Next_State <= V_reg;
-- else
-- if (Count_hit = '1') then
-- Next_state <= V_decrypt;
else
Next_state <= V_wait_sign;
--end if;
end if;
end case;
end process;
end Behavioral;
I can't understand what could be wrong. When I try the testbench, it seems to work.
But tjan on the FPGA it freezes on that state. It is as if he did not receive the signal "Count Hit" from the "SignReg". But I'm not sure about that
i am making a midi interface. UART works fine, it sends the 8 bit message along with a flag to a control unit. When the flag goes high, the unit will store the message in a register and make a clr_flag high in order to set the flag of UART low again. The problem is that i can not make this clr_flag one period long. I need it to be ONE period long, because this signal also controls a state machine that indicates what kind of message is being stored (note_on -> key_note -> velocity, for example).
My question here is, how can a signal (flag in this case) trigger a pulse just for one clk period? what i have now makes almost a pulse during a clock period, but i does it twice, because the flag has not become 0 yet. ive tried many ways and now i have this:
get_data:process(clk, flag)
begin
if reset = '1' then
midi <= (others => '0');
clr_flag <= '0';
control_flag <= '0';
elsif ((clk'event and clk='1') and flag = '1') then
midi <= data_in;
clr_flag <= '1';
control_flag <= '1';
elsif((clk'event and clk='0') and control_flag = '1') then
control_flag <= '0';
elsif((clk'event and clk='1') and control_flag = '0') then
clr_flag <= '0';
end if;
end process;
the problem with this double pulse or longer than one period pulse(before this, i had something that made clr_flag a two period clk pulse), is that the system will go though two states instead of one per flag.
so in short: when one signal goes high (independent of when it goes low), a pulse during one clock period should be generated.
thanks for your help.
The trick to making a single cycle pulse is realising that having made the pulse, you have to wait as long as the trigger input is high before getting back to the start. Essentially you are building a very simple state machine, but with only 2 states you can use a simple boolean to tell them apart.
Morten is correct about the need to adopt one of the standard patterns for a clocked process; I have chosen a different one that works equally well.
get_data:process(clk, reset)
variable idle : boolean;
begin
if reset = '1' then
idle := true;
elsif rising_edge(clk) then
clr_flag <= '0'; -- default action
if idle then
if flag = '1' then
clr_flag <= '1'; -- overrides default FOR THIS CYCLE ONLY
idle <= false;
end if;
else
if flag = '0' then
idle := true;
end if;
end if;
end if;
end process;
There are several issues to address in order to make the design for a one cycle
pulse using flip flops (registers).
First, the use of flip flops in hardware through VHDL constructions typically
follows a structure like:
process (clk, reset) is
begin
-- Clock
if rising_edge(clk) then
-- ... Flip flops to update at rising edge
end if;
-- Reset
if reset = '1' then
-- Flip flops to update at reset, which need not be all
end if;
end process;
So the get_data process should be updated accordingly, thus:
Sensitivity list should contain only clock (clk) and reset
The nested structure with if on event should be as above
Only rising edge of clk should be used, thus no check on clk = '0'
Making a one cycle pulse on clr_flag when flag goes high can be made with a
synchronous '0' to '1' detector on flag, using a version of flag that is
delayed a single cycle, called flag_ff below, and then checking for (flag =
''1) and (flag_ff = '0').
The resulting code may then look like:
get_data : process (clk, reset) is
begin
-- Clock
if rising_edge(clk) then
flag_ff <= flag; -- One cycle delayed version
clr_flag <= '0'; -- Default value with no clear
if (flag = '1') and (flag_ff = '0') then -- Detected flag going from '0' to '1'
midi <= data_in;
clr_flag <= '1'; -- Override default value making clr_flag asserted signle cycle
end if;
end if;
-- Reset
if reset = '1' then
midi <= (others => '0');
clr_flag <= '0';
-- No need to reset flag_ff, since that is updated during reset anyway
end if;
end process;
Synchronisation and Edge Detection for FSM
The Rise, Edge and Fall outputs will strobe for one cycle when those events are detected. Inputs and outputs are synchronised for use with a Finite State Machine.
entity SynchroniserBit is
generic
(
REG_SIZE: natural := 3 -- Default number of bits in sync register.
);
port
(
clock: in std_logic;
reset: in std_logic;
async_in: in std_logic := '0';
sync_out: out std_logic := '0';
rise_out: out std_logic := '0';
fall_out: out std_logic := '0';
edge_out: out std_logic := '0'
);
end;
architecture V1 of SynchroniserBit is
constant MSB: natural := REG_SIZE - 1;
signal sync_reg: std_logic_vector(MSB downto 0) := (others => '0');
alias sync_in: std_logic is sync_reg(MSB);
signal rise, fall, edge, previous_sync_in: std_logic := '0';
begin
assert(REG_SIZE >= 2) report "REG_SIZE should be >= 2." severity error;
process (clock, reset)
begin
if reset then
sync_reg <= (others => '0');
previous_sync_in <= '0';
rise_out <= '0';
fall_out <= '0';
edge_out <= '0';
sync_out <= '0';
elsif rising_edge(clock) then
sync_reg <= sync_reg(MSB - 1 downto 0) & async_in;
previous_sync_in <= sync_in;
rise_out <= rise;
fall_out <= fall;
edge_out <= edge;
sync_out <= sync_in;
end if;
end process;
rise <= not previous_sync_in and sync_in;
fall <= previous_sync_in and not sync_in;
edge <= previous_sync_in xor sync_in;
end;
Below is a way of creating a signal (flag2) that lasts exactly one clock period from a signal (flag1) that lasts at least one clock period.
I don't program in VHDL~ here is what I usually do for the same propose in Verilog:
always #(posedge clk or negedge rst) begin
if(~rst) flgD <= 1'b0;
else flgD <= flg;
end
assign trg = (flg^flgD)&flgD;
I am new to verilog and this is the sample code, which I used for triggering. Hope this serves your purpose. You can try same logic in VHDL.
module main(clk,busy,rd);
input clk,busy; // busy input condition
output rd; // trigger signal
reg rd,en;
always #(posedge clk)
begin
if(busy == 1)
begin
rd <= 0;
en <= 0;
end
else
begin
if (en == 0 )
begin
rd <= 1;
en <= 1;
end
else
rd <= 0;
end
end
endmodule
The below verilog code shall hold the value for the signals for one clock cycle exactly.
module PulseGen #(
parameter integer BUS_WIDTH = 32
)
(
input [BUS_WIDTH-1:0] i,
input clk,
output [BUS_WIDTH-1:0] o
);
reg [BUS_WIDTH-1:0] id_1 = 0 ;
reg [BUS_WIDTH-1:0] id_2 = 0 ;
always #(posedge clk)begin
id_1 <= i;
id_2 <= id_1;
end
assign o = (id_1 & ~id_2);
The way to achieve this is to create a debounce circuit. If you need a D flip-flop to change from 0 to 1, only for the first clock, just add an AND gate before its input like the image below:
So here you can see a D flip-flop and its debounce circuit.
P.S. Circuit created using this.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--input of minimum 1 clock pulse will give output of wanted length.
--load number 5 to PL input and you will get a 5 clock pulse no matter how long input is.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity fifth is
port (clk , resetN : in std_logic;
pdata : in integer range 0 to 5; --parallel data in. to choose how many clock the out pulse would be.
din : in std_logic;
dout : out std_logic
) ;
end fifth ;
architecture arc_fifth of fifth is
signal count : integer range 0 to 5;
signal pl : std_logic; --trigger detect output.
signal sample1 : std_logic;
signal sample2 : std_logic;
--trigger sync proccess.
begin
process(clk , resetN)
begin
if resetN = '0' then
sample1<='0';
sample2<='0';
elsif rising_edge(clk) then
sample1<=din;
sample2<=sample1;
end if;
end process;
pl <= sample1 and (not sample2); --trigger detect output. activate the counter.
--counter proccess.
process ( clk , resetN )
begin
if resetN = '0' then
count <= 0 ;
elsif rising_edge(clk) then
if pl='1' then
count<=pdata;
else
if count=0 then
count<=count;
else
count<=count-1;
end if;
end if;
end if ;
end process ;
dout<='1' when count>0 else '0';--output - get the wanted lenght pulse no matter how long is input
end arc_fifth ;
The full error message is:
ERROR:HDLCompiler:377 - "C:/Users/einar/Documents/Xilinx/ISE/Projects/EDA385/scale_clock_tb.vhd" Line 17: Entity port d does not match with type unsigned of component port
I'm using ISE web pack and I have implemented the top module, the top module is scale_clock.
Also, it simulates just fine when I do behavioral simulation. But for post-map or post-route I get the error message above.
This is the code for the component:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-----------------------------------------
-- scale_clock entity declaration --
-----------------------------------------
ENTITY scale_clock IS
GENERIC (n_bits : INTEGER := 10);
PORT
(
clk_i : IN STD_LOGIC;
load : IN STD_LOGIC;
d : IN UNSIGNED (n_bits-1 DOWNTO 0) := (OTHERS => '0');
clk_o : OUT STD_LOGIC
);
END scale_clock;
----------------------------------------------
-- scale_clock architecture definition --
----------------------------------------------
ARCHITECTURE behavioral OF scale_clock IS
SIGNAL new_clk : STD_LOGIC := '0';
BEGIN
clk_o <= new_clk;
clk_gen: PROCESS(clk_i, load, d) -- Should load and d be in the stvty list? --
VARIABLE cnt : UNSIGNED (n_bits-1 DOWNTO 0) := (0 => '1', OTHERS => '0');
VARIABLE top : UNSIGNED (n_bits-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (rising_edge(clk_i)) THEN
IF (load = '1') THEN
-- Syncrounous load of prescaler value. --
top := d;
cnt := (0 => '1', OTHERS => '0');
new_clk <= '0';
ELSIF (cnt = top) THEN
cnt := (0 => '1', OTHERS => '0');
new_clk <= NOT new_clk;
ELSE
-- Count up. --
cnt := cnt + 1;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
And this is the testbench:
-- TestBench Template
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY scale_clock_testbench IS
END scale_clock_testbench ;
ARCHITECTURE behavior OF scale_clock_testbench IS
-- Component Declaration
COMPONENT scale_clock
PORT
(
clk_i : IN STD_LOGIC;
load : IN STD_LOGIC;
d : IN UNSIGNED (9 DOWNTO 0) := (OTHERS => '0');
clk_o : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk_i : STD_LOGIC := '0';
SIGNAL load : STD_LOGIC := '0';
SIGNAL d : UNSIGNED (9 DOWNTO 0) := (OTHERS => '0');
SIGNAL clk_o : STD_LOGIC := '0';
CONSTANT CLK_PERIOD : TIME := 10 ns;
BEGIN
-- Component Instantiation
uut: scale_clock PORT MAP
(
clk_i => clk_i,
load => load,
d => d,
clk_o => clk_o
);
clk_process : PROCESS
BEGIN
clk_i <= '0';
WAIT FOR CLK_PERIOD/2;
clk_i <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
-- Test Bench Statements
tb : PROCESS
BEGIN
WAIT FOR 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
WAIT FOR CLK_PERIOD * 3;
d <= ("0100101100"); -- decimal 300 in binary --
load <= '1';
WAIT FOR CLK_PERIOD * 1;
load <= '0';
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
I'm new to VHDL but to me they seem to match just fine. Please advice.
The problem is (almost) correctly identified in Tsukuyo's answer. Namely that the OUTPUT from synthesis (and P&R) contains std_logic[_vector] everywhere, and if you try to simulate these files, your testbench connections need to match their types.
Xilinx tools try to force a terrible solution on you, namely to use std_logic[_vector] everywhere instead of making the design and testbench actually reflect the design's intent. To the extent that if you let it auto-generate a testbench for a module, it will "helpfully" convert all your port types (often incorrectly if you use enumerations or records!) into std_logic[_vector].
A better solution (IMO) is to write both your modules and testbench the way they ought to be - namely at the highest level you can (instead of wasting time messing around at low level). Not only unsigned, but enumerations, integers, booleans and records are synthesisable.
Then (if you need to do a post-route simulation) write a simple wrapper around the auto-generated std_logic version, which converts all its ports to the correct types, and instantiate that wrapper in your testbench.
See here.
Cite: The problem is that, for synthesizing, Xilinx assumes every port is either of type std_logic or std_logic_vector (as it generates a new VHDL file that executed the synthesized model, including precise timing simulation). In order for it to work with a synthesizer, you should change the entity definition.
I want to use four push buttons as inputs and three seven-segment LED displays as outputs. Two push buttons should step up and down through the sixteen RAM locations; the other two should increment and decrement the contents of the currently-displayed memory location. I am now trying to simulate my design using ModelSim test benches, with button presses. Here is what I believe to be the relevant portions of my code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DE2_TOP is
port (
KEY : in std_logic_vector(3 downto 0); -- Push button
);
end DE2_TOP;
architecture datapath of DE2_TOP is
begin
U1: entity work.lab1 port map (
key => key,
);
end datapath;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity raminfr is -STANDARD RAM INFERENCE
port (
clk : in std_logic;
we : in std_logic;
a : in unsigned(3 downto 0);
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0)
);
end raminfr;
architecture rtl of raminfr is
type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;
signal read_a : unsigned(3 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(to_integer(a)) <= di;
end if;
read_a <= a;
end if;
end process;
do <= RAM(to_integer(read_a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab1 is
port(
clock : in std_logic;
key : in std_logic_vector(3 downto 0);
);
end lab1;
architecture up_and_down of lab1 is
signal value_in_ram : unsigned(7 downto 0);
signal clk : std_logic;
signal we : std_logic;
signal value_counter : unsigned(7 downto 0) ;
signal register_counter : unsigned(3 downto 0);
begin
U1: entity work.raminfr port map (
a => register_counter,
di => value_counter,
do => value_in_ram,
clk => clk,
we => we
);
process(clock)
begin
if rising_edge(clock) then
if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
value_counter <= value_counter + "1";
elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then
value_counter <= value_counter - "1";
elsif (key(3)='1' and key(2)='0' and key(1)='0' and key(0)='0') then
register_counter<= register_counter + "1";
value_counter <= value_in_ram;
elsif (key(3)='0' and key(2)='1' and key(1)='0' and key(0)='0') then
register_counter<= register_counter - "1";
value_counter <= value_in_ram;
end if;
end if;
end process;
end architecture up_and_down;
The problem is that despite initializing "key" (the buttons) in my test bench, ModelSim still lists the object as "UUUU". Here is the code for my test bench, which is located in a separate file:
library ieee;
use ieee.std_logic_1164.all;
entity DE2_TOP_TEST is
end;
architecture BENCH of DE2_TOP_TEST is
signal KEY : std_logic_vector(3 downto 0);
begin
KEY<="0010";
U1: entity work.DE2_TOP port map (
key=>key,
);
end BENCH;
Anyone know what's wrong?
You use registers in your design. So you need to add a signal to your clock input:
constant tb_clk_period : time := (1 sec) / 10_000_000; -- 10 MHz
signal tb_clk : std_ulogic := '0';
...
-- clock generator
tb_clk <= not tb_clk after tb_clk_period / 2;
I'm new to VHDL and confused with this design
when Acknwledgement= '1' and clk='1' then
count should be count+1;
and when Acknwledgement= '0' my total counted value of clocks should be assigned to the 'output' and after that resetting count='0' and output='0'.
can anyone help with this.
Thanks in advance.
EDIT:
Code from comment pasted in:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity acknw is
port (acknw : in std_logic;
clk : in std_logic;
output : out integer range 0 to 15);
end acknw;
architecture Behavioral of acknw is
begin
process(clk, acknw) variable c : integer range 0 to 15;
begin
if(clk'event and clk = '1') then
if(acknw = '1') then
c := c+1;
output <= c;
else
c := 0;
output <= c;
end if;
end if;
end process;
end Behavioral;
from your comment it sounds like you want an asynchronous acknw, try something like this:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity acknw is
port (acknw : in std_logic;
clk : in std_logic;
output : out integer range 0 to 15);
end acknw;
architecture Behavioral of acknw is
begin
process(clk, acknw)
begin
if (acknw = '0') then
output <= 0;
elsif rising_edge(clk) then
-- rollover
if (output /= 15) then
output <= output + 1;
else
output <= 0;
end if;
end if;
end process;
end Behavioral;