System Verilog Conditional Type Definition - typedef

Question

Is there a way to conditionally select between two types based on a parameter value?
typedef struct packed {
logic a;
} my_type_1_t;
typedef struct packed {
logic [1:0] a;
} my_type_2_t;
parameter type type_t = my_type_1_t;
if (MY_PARAM == 1) begin
typedef my_type_1_t type_t;
do something...
end else begin
typedef my_type_2_t type_t;
do the same something as above with different struct...
end
type_t my_signal;
As you can see, I need to do the same operations in the else clause as in the if clause, but on a different struct. This seems redundant to me, and I am curious if there is a way to avoid duplication.

Answer 1

No, you can't do this because the type_t name will be local to the generate-if block. But it wouldn't make much sense if you could because code that references my_signal is going to want to access my_signal.b and it would not exist in certain cases.

Answer 2

The only way to mimic the behavior you want is to use parameterized modules.
Here is a simple example:
typedef struct {
logic a, b;
} type1_t;
typedef struct {
logic [1:0] a1, b1;
} type2_t;
module top(input logic clk);
pmod#(.T(type1_t)) inst1(clk);
pmod#(.T(type2_t)) inst2(clk);
endmodule
module pmod#(type T=int) (input logic clk);
logic [1:0] a, b;
T t;
if ($typename(T) == "type1_t") begin
always #(posedge clk) begin
a = t.a;
b = t.b;
end
end
else if ($typename(T) == "type2_t") begin
always #(posedge clk) begin
a = t.a1;
b = t.b1;
end
end
// do something with a and b
endmodule

Answer 3

First, question to ask yourself is whether you are needing synthesizable code?
If not, you simply can use a parameterized class with different struct definitions, effectively giving you parameterized structs.
Note that it would be possible for synthesis tools to synthesize such code, yet your mileage with each tool varies, and last time I checked, most synthesis tools didn't even support this limited use of class construct as a scoping mechanism.
Packages, which have much more synthesis tool support unfortunately do not have an option for parameterizing packages/structs. The best I've done is to emulate parameterizable structs using macros, e.g.:
// Macro and struct definitions could be moved to common header file if shared across multiple modules
// Acts like a parameterized typedef
// Note: You could even extend multiple nested levels if needed
// This mechanism requires that the struct definitions take the same form, i.e., logic[0:0] instead of just logic
`define my_type_t(W) struct packed { logic [W-1:0] a; }
// module used as example, but would work in most contexts
module mod;
parameter MY_PARAM = 1;
// In a particular parameterized context, can resolve the macro
// into a real typedef if desired
typedef my_type_t(MY_PARAM) type_t;
type_t my_signal;
// do something that works with either struct definition
endmodule;
Please check my syntax above as I took a previously working example and modified it to match the question from OP, without testing final code segment.