A system has 512MB physical memory and 4GB virtual memory with a page size of
8KB. (Sznarks)
Find the number of bits for the physical address and the virtual address.
Find the number of pages and the number of frames.
Find the number of bits for the physical address and the virtual address.
The physical address space needs to be large enough for more than just RAM (you need space for ROM and memory mapped devices; and often there's "unused" space for future expansion). There isn't enough information to say anything other than "physical addresses probably have more than 29 bits", but in that case it's likely that the hardware designer would round it up to a nice "power of 2", so 32 bits is the most likely for number of bits in a physical address.
Virtual addresses would have 32 bits (because "log2(4 GiB) == 32").
Find the number of pages and the number of frames.
"512 MiB / 8 KiB" works out to 65536 physical pages of RAM alone (excluding ROM, memory mapped devices, etc).
"4 GiB / 8 KiB" works out to a maximum of 524288 virtual pages per virtual address space.
Related
Suppose the following properties are given:
32-bit virtual address
16-kbyte virtual page size
32-bit Page Table Entry
8-Gbyte physical memory
(that 1Gb = 230 bytes and 1 kb = 210 bytes)
Does this mean that the page table must have 2^20=1048576? And how can I calculate its physical frame and virtual page?
The physical page size must match the virtual page size (16 KiB).
With 8 GiB of physical memory divided into 16 KiB pages; you'd end up with 524288 pages of physical RAM. However, the physical address space is also used things that aren't RAM (ROM, memory mapped devices, etc), and often some physical memory is "stolen" for other purposes (e.g. integrated graphics) and made inaccessible via. any normal physical addresses. With this in mind the correct answer is "the number of physical frames is unknowable, there isn't enough information".
If virtual addresses are 32-bit, then the virtual address space size is 4 GiB. With 4 GiB of virtual address space divided into 16 KiB pages you'd end up with 262144 virtual pages per virtual address space. However; there are an unknowable number of virtual address spaces (and an unknowable amount of each virtual address space will probably be used as "kernel space that is the same in all virtual address spaces"); so the correct answer is "the total number of virtual pages (for all virtual address spaces) is unknowable, there isn't enough information".
I am new to the concept of virtual memory.
I will like to know whats the maximum space of memory a procces can use through virtual memory?
Is it available RAM + available swap space ??
(This question has already been asked but people had different opinions on this issue)
For most systems the maximum size of virtual memory is determined by the number of bits in a virtual address that are supported by the MMU.
For example; for typical 64-bit 80x86 CPUs a virtual address is 64 bits, but only the lowest 48 bits are supported by the MMU, so the virtual address size is 1 << 48 = 256 TiB. Everything else (amount of RAM, swap space, etc) doesn't matter.
In theory, you can (e.g.) fill the entire virtual address space by mapping the same page of RAM everywhere; and (for 64-bit 80x86) it would only cost 4 KiB of RAM (for the data that's mapped everywhere) plus another 16 KiB of RAM (for MMU's own data - page tables, etc). In other words, a measly 20 KiB of physical RAM is enough to fill a whopping 256 TiB of virtual space.
Of course for practical purposes often the kernel reserves some of the virtual address space (e.g. half of it), so a process can only use the remainder (e.g. 128 TiB); and (for modern 64-bit CPUs) unless you're mapping the same data at different places in the virtual address space (which would be silly/pointless) it's likely that you'll run out of things to put in a virtual address space before you run out of virtual address space.
This isn't the case for older 32-bit CPUs, where the virtual address space is a lot smaller (where maybe a process can only use 2 GiB out of a 4 GiB total space) and it's a lot easier to run out of space.
Why the Operative System of 32 bits has the limitation of 4 GB of RAM?. I know the processor has a register, the PC(Program Counter), where the adress of an instruction is located and if this register is of 32 bits, its a hardware limitation because of size of the register. But why the Operative System of 32 bits has this limitation? Its harcoded in its kernel that the maximum ram avalaible can be 2 exponent 32 bits?
Thanks
Why the Operative System of 32 bits has the limitation of 4 GB of RAM?
It probably doesn't.
"32-bit" typically refers to the size of general purpose registers and may have nothing to do with the size of any address. For example, for modern 64-bit operating systems addresses are often only 48 bits.
Also; most operating systems use some form of paging where virtual address size may have nothing to do with physical address size. For example; for 32-bit 80x86 using PAE (Physical Address Extensions); virtual addresses are limited to 32-bit (causing each process to be limited to 4 GiB of "virtual space", minus whatever kernel reserves for itself); but physical addresses are/were 36 bits (giving a limit of "up to 64 GiB of RAM, minus space used for devices, ROMs, etc").
Even when physical address size is 32-bit, there are other hardware restrictions - e.g. some of those bits may be ignored by the hardware and/or used for other purposes (e.g. one bit used as an "encrypt the RAM or not" flag), and/or not supported by the RAM controller; and some of the physical address space must be used by things that are not RAM (ROM, devices, etc); so it's extremely unlikely that "32-bit physical addresses" will mean "max. of 4 GiB of RAM".
Finally; it is possible for hardware to support bank switching, where RAM is split into banks and some banks are mapped into the physical address space while others are not; and where "which bank/s are selected" is controlled by OS using special hardware. This was very common for 8-bit and 16-bit CPUs (e.g. "expanded memory" cards plugged into an ISA slot in PCs in the early 1980s); but has become significantly less common as physical address sizes have increased.
The limit is because in 32-bit architectures you are referencing the addresses in memory using 32-bit addresses. So this means that in 32-bit architecture you can only reference 2^32 addresses. Next we need to take into consideration that each address means that we are referencing a single byte which is 8 bits. This means that in effect we can reference 2^32 * 8 bits
Now lets get to the mathy part of the answer. If you can reference 2^32 * 8 bits then you can reference 2^35 bits and 2^35 = 34359738368 bits = 4294967296 bytes = 4194304 kilobytes = 4096 megabytes
And that is why you can only reference 4GiB of memory in 32-bit computers.
Essentially, how does 4Gb turn into 4GB? If the memory is addressing Bytes, should not the possibilities be 2(32/8)?
It depends on how you address the data.
If you use 32 bits to address each bit, you can address 232 bits or 4Gb = 512MB. If you address bytes like most current architectures it will give you 4GB.
But if you address much larger blocks you will need less bits to address 4GB. For example if you address each 512-byte block (29 bytes) you can address 4GB with 23 bits. FAT16 uses 16 bits to address (maximum) 64KB clusters and therefore can address a maximum 4GB volume. The same is used in Java Compressed Oops where you can address 32GB of memory with 32-bit reference.
Some older architectures even use word-addressable memory instead of byte like most do nowadays. Modern architectures that have a minimum addressable unit bigger than an octet are mainly found in DSPs. There also a few architectures with bit-addressable memory like Intel 8051
Most modern computers are byte-addressable, with each address identifying a single eight bit byte of storage; data too large to be stored in a single byte may reside in multiple bytes occupying a sequence of consecutive addresses.
There exist word-addressable computers, where minimal addressable storage unit is exactly the processor's word. For example, the Data General Nova minicomputer, and the Texas Instruments TMS9900 and National Semiconductor IMP-16 microcomputers used 16 bit words, and there were many 36-bit mainframe computers (e.g., PDP-10) which used 18-bit word addressing, not byte addressing, giving an address space of 218 36-bit words, approximately 1 megabyte of storage.
The efficiency of addressing of memory depends on the bit size of the bus used for addresses – the more bits used, the more addresses are available to the computer. For example, an 8-bit-byte-addressable machine with a 20-bit address bus (e.g. Intel 8086) can address 220 (1,048,576) memory locations, or one MiB of memory, while a 32-bit bus (e.g. Intel 80386) addresses 232 (4,294,967,296) locations, or a 4 GiB address space.
The electrical interface on the chip consists (extremely simplified) of a wires for the address (e.g. 32 address lines) and wires for the data (e.g. 8 wires for read data coming from the RAM, 8 wires for write data going to the RAM). In this case you have 232 words of 8 bits, so you can address 232*8 bits of data.
If you had a RAM with a word width of 16-bit instead (much more likely than 8-bit) you would be able to address twice as much RAM with the same number of address bits. On a modern system, you cannot really "read one byte" but instead the CPU fetches a whole cache line from the RAM and then gives you back just the byte that you asked for.
You can address 2 fields in memory with 1 bits.
You can address 4 fields in memory with 2 bits.
00, 01, 10, 11
So we can address memory by 2^n. For 32bit memory that each address holds 1byte can address 4GB data.
2^32 = 4.294.967.296 address can hold 4GByte data.
While I was reading this Wikipedia article, http://en.wikipedia.org/wiki/Memory_management_unit#How_it_works, I came across that divide virtual address space (range of address used by processor) into pages. But I have learnt that only the physical memory (RAM) is divided into pages. So how is the division of virtual address space of a process done?
Also, here the definition of virtual address space goes as range of address used by processor. Range of address used by processor means the length of address bus in processor, right? So if I am having a processor of address bus of 32 bits, and a RAM of 4 GB (2^32), is my physical and virtual address space same?
Bear with me if the questions are too naive.. I am still not getting a very clear visualization of address space. Thanks in advance.
The answer is specific to each OS, but in general terms it means that though each process gets say 32 bits worth of addressable memory, this memory space is divided in to ranges or pages of a certain size.
Simplistically speaking when your process accesses an address, that location will be in a certain page. The OS will ensure that there is physical memory that is mapped to that location. However it may not be in the same address in physical ram.
When some other process addresses that location then the OS will map in a page of physical ram at that so that location too will be addressable.
All the time the physical memory pages are being mapped to and from disk (so that you can have memory greater than 32 bits worth_\, and the virtual memory pages are being mapped to physical pages just described.
I really recommend reading the links in this question https://stackoverflow.com/questions/1437914/best-book-on-operating-systems