How to create ROM with VecInit(Array()) in Chisel? - scala

Question

I'm trying to declare a «rom» with VecInit() like it :
val GbColors = VecInit(Array(GB_GREEN0, GB_GREEN1, GB_GREEN2, GB_GREEN3))
With GB_GREENx declared like it :
class VgaColors extends Bundle {
val red = UInt(6.W)
val green = UInt(6.W)
val blue = UInt(6.W)
}
//...
object GbConst {
//...
/* "#9BBC0F"*/
val GB_GREEN0 = (new VgaColors()).Lit(_.red -> "h26".U(6.W),
_.green -> "h2F".U(6.W),
_.blue -> "h03".U(6.W))
/* "#8BAC0F"*/
val GB_GREEN1 = (new VgaColors()).Lit(_.red -> "h1E".U(6.W),
_.green -> "h27".U(6.W),
_.blue -> "h03".U(6.W))
/* "#306230"*/
val GB_GREEN2 = (new VgaColors()).Lit(_.red -> "h0C".U(6.W),
_.green -> "h18".U(6.W),
_.blue -> "h0C".U(6.W))
/*"#0F380F"*/
val GB_GREEN3 = (new VgaColors()).Lit(_.red -> "h03".U(6.W),
_.green -> "h0E".U(6.W),
_.blue -> "h03".U(6.W))
I can't manage to use GbColors as indexable Vec :
io.vga_color := GbColors(io.mem_data)
It generate a java stack error :
[info] [0.004] Elaborating design...
[error] chisel3.internal.ChiselException: Connection between sink (VgaColors(IO in unelaborated MemVga)) and source (VgaColors(Wire in GbWrite)) failed #.blue: Sink or source unavailable to current module.
[error] ...
[error] at gbvga.MemVga.$anonfun$new$42(memvga.scala:87)
[error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
[error] at chisel3.WhenContext.<init>(When.scala:80)
[error] at chisel3.when$.apply(When.scala:32)
[error] at gbvga.MemVga.<init>(memvga.scala:86)
[error] at gbvga.GbVga.$anonfun$memvga$1(gbvga.scala:24)
[error] at chisel3.Module$.do_apply(Module.scala:54)
[error] at gbvga.GbVga.<init>(gbvga.scala:24)
[error] at gbvga.GbVgaDriver$.$anonfun$new$9(gbvga.scala:53)
[error] ... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)
...
To manage it, I have to use switch(){is()} format :
switch(io.mem_data) {
is("b00".U) {
io.vga_color := GB_GREEN0
}
is("b01".U) {
io.vga_color := GB_GREEN1
}
is("b10".U) {
io.vga_color := GB_GREEN2
}
is("b11".U) {
io.vga_color := GB_GREEN3
}
}
But it's too verbose I think.
What is wrong with my VecInit() «rom» ?
[edit]
My versions are :
$ java -version
java version "1.8.0_151"
Java(TM) SE Runtime Environment (build 1.8.0_151-b12)
Java HotSpot(TM) 64-Bit Server VM (build 25.151-b12, mixed mode)
$ scala -version
Scala code runner version 2.11.7-20150420-135909-555f8f09c9 -- Copyright 2002-2013, LAMP/EPFL
In build.sbt :
val defaultVersions = Map(
"chisel3" -> "3.4.0-RC1",
"chisel-iotesters" -> "1.5.0-RC1",
"chisel-formal" -> "0.1-SNAPSHOT",
)

Answer 1

I think the problem here is because the Bundles in GbConst are created outside of a Module. One potential fix would be to make GbConst into a trait and add it to Modules who need access to those values. (I have created a PR that seems to show this approach works, though it's probably creating a lot of copies of the Bundles). Another approach (that I have not tried) would be to create a Module that serves up all the Bundles as outputs (which should make less copies).
My PR also changed the chisel3 and chisel-testers dependencies to be SNAPSHOTS.