I have the following specification for a queue:
------------------------------- MODULE queue -------------------------------
EXTENDS Naturals
CONSTANT L (* The fixed max length of the queue *)
VARIABLE q (* Represents the queue as the number of items in it *)
----------------------------------------------------------------------------
TypeInvariant == q >= 0 /\ q <= L
----------------------------------------------------------------------------
Init == q = 0
NoOp == q' = q (* Queue unchanged *)
Enqueue == q' = q + 1 (* Element added *)
Dequeue == q' = IF q = 0 THEN q ELSE q - 1 (* Element removed *)
Next == NoOp \/ Enqueue \/ Dequeue
----------------------------------------------------------------------------
Spec == Init /\ [][Next]_q
----------------------------------------------------------------------------
THEOREM Spec => TypeInvariant
============================================================================
When I run TLC with the following values for constants:
L <- 3
And these contraints:
INVARIANT
TypeInvariant
It reports these errors:
But the specification allows values in (0 .. L), so why is TLC reporting q=1, q=2, q=3, q=4 as invalid states?
The error trace output is the following:
<<
[
_TEAction |-> [
position |-> 1,
name |-> "Initial predicate",
location |-> "Unknown location"
],
q |-> 0
],
[
_TEAction |-> [
position |-> 2,
name |-> "Enqueue",
location |-> "line 18, col 12 to line 18, col 21 of module queue"
],
q |-> 1
],
[
_TEAction |-> [
position |-> 3,
name |-> "Enqueue",
location |-> "line 18, col 12 to line 18, col 21 of module queue"
],
q |-> 2
],
[
_TEAction |-> [
position |-> 4,
name |-> "Enqueue",
location |-> "line 18, col 12 to line 18, col 21 of module queue"
],
q |-> 3
],
[
_TEAction |-> [
position |-> 5,
name |-> "Enqueue",
location |-> "line 18, col 12 to line 18, col 21 of module queue"
],
q |-> 4
]
>>
How is one supposed to recognize those that are considered errors and those which are not from this trace? The interface shows no red light on q=0.
A red cell indicates that the value of the variable changed in this state compared to its previous value (see https://tla.msr-inria.inria.fr/tlatoolbox/doc/model/executing-tlc.html). Red does not indicate that states are not valid!
The prefix of an (infinite) behavior -reported by the trace explorer as an error trace- does not satisfy the (safety) property TypeInvariant because TypeInvariant does not allow q=4.
By the way, the TLA+ group is a much better place to ask questions.
Related
I have to write a single SVA for the complete protocol shown in this image
I wrote the following SVA but it doesn't capture the immediate ack. How do I fix that
#(posedge clk)
$rose(val) |=>
( $stable(data) && !ack && val ) ##[1:64] ( ack && val ) ##1 ( !ack && !val )
Looking at your assertion, it won't capture the immediate ACK because you are expecting a sequence excluding an immediate ACK with !ack. I would re-write your assertion as:
sequence seq;
$stable({address, data}) ##[0:63] (val && ack && $stable({address, data})) ##1 !ack ##1 !val;
endsequence
property p;
#(posedge clk)
$rose(val) |=> seq;
endproperty
as_protocol : assert property(p);
I want assertion that if in current cycle signal 'a' equal to "0110"(in binary) in the next cycle signal'b'not bigger than 31(it should be between 0 and 31.it should be less than 00000000000000000000000000011111)(its width equal 32)
Can everyone help me to write assertion?!
Excuse me for my bad english.
assert property ( # (posedge clk ) (a == 32'b0110) |=> ( b > 32'd0 && b < 32'd32 ) );
assert - will set the property( assertion ) into action. The property has to be based on a clock . Choose the appropriate clock which is triggering the registers a & b in the design. Implication operator |=> indicates that the property has to be true in the next clock cycle. In this case if a equals 6, the next cycle b has to between 0 and 32 ).
In case of a failure some similar message ( based on the simulator ) will be displayed.
top.unnamed$$_0: started at ns failed at ns
Offending '((b > 0) && (b < 32))'
You can read up a basic tutorial on assertions
https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/
property clk_req_check;
#(posedge upbm_clk) disable iff (~upbm_reset_n)
//#(posedge upbm_clk);
case (sb_adrc)
2'b00 : 1'b1 |-> (clk_req[0] == 1'b1) [*] (sb_adrc != 2'b00);
2'b01 : 1'b1 |-> (clk_req[1] == 1'b1) [*] (sb_adrc != 2'b01);
2'b10 : 1'b1 |-> (clk_req[2] == 1'b1) [*] (sb_adrc != 2'b10);
2'b11 : 1'b1 |-> (clk_req[3] == 1'b1) [*] (sb_adrc != 2'b11);
default : 1'b0;
endcase
endproperty: clk_req_check
** Error: (vlog-13069) cad_property.sv(5): near "case": syntax error, unexpected case.
without disable_iff
** Error: (vlog-13069) cad_property.sv(3): near "case": syntax error, unexpected case, expecting disable.
case/endcase within an assertion may not supported in your version of Questa.
That's interesting, I've never tried writing a case statement inside a concurrent assertion, not sure if that is allowed. Thinking about it though, you want to simultaneously be checking all 4 values of sb_adrc with concurrent assertions (which run constantly on every upbm_clk), which feels to me that you need 4 separate concurrent assertions. Each one similar to the following:
property clk_req_check;
#(posedge upbm_clk) disable iff (~upbm_reset_n)
sb_adrc == 2'b00 |-> (clk_req[0] == 1'b1) ##1 (sb_adrc != 2'b00)
endproperty
This Systemverilog tutorial lists interesting always block event control statements that utilize the iff qualifier.
I don't understand the first 3 simulation results for #1 and #2:
#0 clk 0 rst 0 enable x d x q x latch x
#1 clk 1 rst 0 enable x d 0 q 0 latch x
Reset is asserted with iff
Reset is asserted, no iff
#2 clk 0 rst 1 enable x d 0 q 0 latch x
Reset is asserted, no iff
Namely, why is reset triggering the $display statements #1 when there hasn't been a posedge rst?
Also, why isn't $display(Reset is asserted with iff) triggered #2 when rst becomes 1?
The $display() messages are being printed at time #2. The simulator scheduler executes the $display() messages when the lines are reached. The $monitor() message is only printed at the end of the time step. Therefore, within the same time step, $display() messages will be printed before the $monitor() message. Add $time to the $display messages to help visualize this.
The final Reset is asserted, no iff is not part of time 2, but time 3. When the clock has a rising.
#3 clk 1 rst 1 enable x d 0 q 0 latch x
The "with iff" message is not displayed because iff rst == 0 masks the posedge clk from being observed when rst !=0. The posedge clk can only be observed when iff condition is true.
Do note that iff is not synthesizable, so do not put it in a design. The feature is for verification and behavioral modeling.
I am working on a project(I have to implement it in Perl but I am not good at it) that reads DNA and finds its RNA. Divide that RNA's into triplets to get the equivalent protein name of it. I will explain the steps:
1) Transcribe the following DNA to RNA, then use the genetic code to translate it to a sequence of amino acids
Example:
TCATAATACGTTTTGTATTCGCCAGCGCTTCGGTGT
2) To transcribe the DNA, first substitute each DNA for it’s counterpart (i.e., G for C, C for G, T for A and A for T):
TCATAATACGTTTTGTATTCGCCAGCGCTTCGGTGT
AGTATTATGCAAAACATAAGCGGTCGCGAAGCCACA
Next, remember that the Thymine (T) bases become a Uracil (U). Hence our sequence becomes:
AGUAUUAUGCAAAACAUAAGCGGUCGCGAAGCCACA
Using the genetic code is like that
AGU AUU AUG CAA AAC AUA AGC GGU CGC GAA GCC ACA
then look each triplet (codon) up in the genetic code table. So AGU becomes Serine, which we can write as Ser, or
just S. AUU becomes Isoleucine (Ile), which we write as I. Carrying on in this way, we get:
SIMQNISGREAT
I will give the protein table:
So how can I write that code in Perl? I will edit my question and write the code that what I did.
Try the script below, it accepts input on STDIN (or in file given as parameter) and read it by line. I also presume, that "STOP" in the image attached is some stop state. Hope I read it all well from that picture.
#!/usr/bin/perl
use strict;
use warnings;
my %proteins = qw/
UUU F UUC F UUA L UUG L UCU S UCC S UCA S UCG S UAU Y UAC Y UGU C UGC C UGG W
CUU L CUC L CUA L CUG L CCU P CCC P CCA P CCG P CAU H CAC H CAA Q CAG Q CGU R CGC R CGA R CGG R
AUU I AUC I AUA I AUG M ACU T ACC T ACA T ACG T AAU N AAC N AAA K AAG K AGU S AGC S AGA R AGG R
GUU V GUC V GUA V GUG V GCU A GCC A GCA A GCG A GAU D GAC D GAA E GAG E GGU G GGC G GGA G GGG G
/;
LINE: while (<>) {
chomp;
y/GCTA/CGAU/; # translate (point 1&2 mixed)
foreach my $protein (/(...)/g) {
if (defined $proteins{$protein}) {
print $proteins{$protein};
}
else {
print "Whoops, stop state?\n";
next LINE;
}
}
print "\n"
}