Implementing Montogomery Modular Reduction/Multiplication (MMM) - rsa

Question

I have been trying to implement Montogomery Modular Reduction in Verilog and encountered an error while doing so. Attaching the code below-
module MMM ( a , b , c , y ) ;
// Parameters
//
parameter N = 32 ; // Default value of N
// Inputs
//
input [N-1:0] a ; // N-bit input a
input [N-1:0] b ; // N-bit input b
input [N-1:0] c ; // N-bit input c
// Outputs
//
output [N-1:0] y ; // N-bit output y
// Internal nets
//
wire [N-1:0] q ; // N-bit q array
//wire [N+1:0] t [0:N-1] ; // (N+2)-bit temporary iteration variable t, bus array of N
wire [N+1:0] s ; //
// Initial value of S
//
assign s[0] = 0 ;
// Iteration
//
genvar i ;
generate
for ( i = 0 ; i <= N-1 ; i = i + 1 )
begin : iterate
assign q[i] = (s[i] + a[i] * b) % 2;
assign s[i+1] = (s[i] + q[i] * c + a[i] * b) / 2;
if (s[N] >= c)
assign y = s[N] - c ;
else
assign y = s[N] ;
end // iterate
endgenerate
//assign MMM[a, b, c] = y;
endmodule
The error- The generate if condition must be a constant expression.
Any help would be great.
Thanks

Answer 1

The problem is that if inside a generate must be decidable at compilation time, you are using a signal as a condition of the if block. I understand that what you mean is to create a mux with that expression in the selector, but the compiler don't.
you could wrap the iterate logic in a procedural always block and then you would be able to use the if statement.
Also, the assignment to y should be outside the iterate block, otherwise it will have multiple drivers.
Fixing these two problems you have
module MMM ( a , b , c , y ) ;
// Parameters
//
parameter N = 32 ; // Default value of N
// Inputs
//
input [N-1:0] a ; // N-bit input a
input [N-1:0] b ; // N-bit input b
input [N-1:0] c ; // N-bit input c
// Outputs
//
output [N-1:0] y ; // N-bit output y
// Internal nets
//
wire [N-1:0] q ; // N-bit q array
//wire [N+1:0] t [0:N-1] ; // (N+2)-bit temporary iteration variable t, bus array of N
wire [N+1:0] s ; //
// Initial value of S
//
assign s[0] = 0 ;
// Iteration
//
genvar i ;
generate
for ( i = 0 ; i <= N-1 ; i = i + 1 )
begin : iterate
assign q[i] = (s[i] + a[i] * b) % 2;
assign s[i+1] = (s[i] + q[i] * c + a[i] * b) / 2;
end // iterate
endgenerate
assign y = s[N] >= c ? s[N] - c : s[N];
//assign MMM[a, b, c] = y;
endmodule
Disclaimer: Maybe there are more errors, I did not notice.