I have a number of signals that I would like to verify the delay between them.
For example, lets define register with the name X_Y_DELAY which configure the time should pass from the rise of X signal to Y signal.
I want to make sure that the value I write to the X_Y_DELAY register is really the time between the signal increases.
I wonder if the right way is to do it through the uvm scoreboard or through the monitor while the signals arrive?
Thanks
This is really best done in an assertion within the interface itself.
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Assume that you have a Simulink simulation where a certain signal is first positive and after some time t in a given interval, it becomes negative. Your goal is to find the zero-crossing.
A first approach would be to plot the signal over the given interval, save it and calculate the zero-crossing.
When repeating this simulation numerous times for varying parameters, it would be beneficial to be able to stop the simulation after the signal has become negative. Then there is already enough information for the calculation of the zero-crossing in Matlab. How could you do that?
Yes, use the Stop Simulation block with the appropriate logical input to the block:
You can use an if / else block to control the flow in the Simulink model. In the if / else block, you can choose the condition if u > 0, continue as normal if it's true, and use the else-option to bypass the rest of the flow you would otherwise run. For instance jump directly to the scope.
Another ways:
You can use Hit Crossing Block in Simulink to find time at the moment of hitting zero.
Another way - use any Trigger or Resettable system. It detects the zero crossing too. For example: this question at SO.
Of course you can also use User Defined function to detect zero crossing by your hand and do whatever you want with the signal at the same time.
About making a lot of simulations and then stops:
you can use Check Upper Static Bound for automatically stops simulation at the moment when zero will be crossed in nth time. For example:
I set upper bound = 10 for this block and this stops at 10th crossing.
There are a lot of ways to save function values in this points or just array of times but this is an another question :)
I am new with signal processing, i have following signals which i've got after some pre-processing on original signals.
You can see some of them has some similarities with others and some doesn't. but the problem is They have various range(in this example from 1000 to 3000).
Question
How can i analysis their properties scale-free(what i mean from properties is statistical properties of signals or whatever)??
Note that i don't want to cross-comparing the signals, i just want independent signals signatures which i can run some process on them sometime later.
Anything would help.
If you want to make a filter that separates signals that follow this pattern from signals that don't, well, there's tons of things you could do!
Just think practically. As a first shot at it, you could do something like this (in this order):
Check if the signals are all-positive
Check if the first element is close in value to the last element
Check if the maximum lies "in the middle" somewhere
Check if the first value is small, then the signal grows, then shrinks again
Check if the growth rates are gradual. You could for example analyze their derivatives (after smoothing):
a. derivative should be all-positive for a while, then all-negative.
b. derivative should be smooth (no jumps greater than some tolerance)
Without additional knowledge about the signal's nature/origin, it's going to be hard to come up with more meaningful metrics than these...
I am verifying part of a design which generates pulses with precisely timed edges. I have a basic behavioral model which produces an output which is similar, but not exactly the same as the design. The differences between the two are smaller than the precision needed for the design, so my model is good enough. The problem is: how do I do a comparison between these two signals?
I tried:
assert(out1 == out1_behav);
But that fails since the two signals have edges which happen 1ps apart. The design only requires that the edges be placed with 100ps precision, so I want a pass in this situation.
I thought about using a specify block with $delay() timing checks, however this causes me other problems since I need to run with +no_timing_checks to keep my ram models from failing in this RTL sim.
Is there a simple way to check that these edges are "almost" the same?
With the design requirement for the the signals to match within 100ps you could add a compare logic will a 100ps transition delay to act as a filter.
bit match;
assign #100ps match = (out1 == out1_behav);
always #*
assert #0 (match==1);
Verilog has different ways of assigning delay: transition and transport. Transition delays control the rise, fall, and indeterminate/high-Z timing. They can act as a filter if a driving signal gives a pulse less then the delay. Transport delays will always follow the the driving signals with a time shift. When the delays are large transition and transport will look the same.
assign #delay transition = driver; // Transition delay
always #(rhs) transport <= #dealy driver; // Transport delay
example: http://www.edaplayground.com/s/6/878, click the run button to see the waveform.
If you are using Modelsim/Questa, you can still use +notimingchecks, and then use the tcl command tchech_set to turn on individual timing checks, like $fullskew
Otherwise you will have to write a behavioral block that records the timestamps of the rising and falling edges of the two signals and checks the absolute value of the difference.
I have a matlab function block (which is not relevant) whose input is his previous output (loop). For example, if in a sample period the output is X, his input in the next sample period will be X, and so on.
This image shows a simplification of my simulation. I initialize the input of my function for the first loop.
The problem is that matlab functions recieves an event based signal from de initialization block in the first sample period (zero-duration), which I must convert to a timed based signal (so I can apply the unit delay that avoids an inifite loop, and allows to generate the next input as explained before). So, when I do so, I lose the information contained in the event-based signal (due to the zero-duration values) and the loop does not work.
If there was a way to intialize the loop in the time-based domain (green part of the image) so, in the first sample time, it is not a zero-duration signal, it would avoid the problem.
Is there any way to do so? Or, a different approach for this problem?
Two approaches come to mind
The initial condition can be set in the Unit Delay block, so it's not clear from your simplified example why you need the specific Initialization block.
You could just use a persistent variable inside the MATLAB Function block to maintain the state from one execution of the block to the next (noting that since it is event driven the block may not get called at every time step, only at each event triggger).
I have designed a signal by using the Signal Builder block in Simulink. During the run of my simulation, the signal builder is to restart depending on the satisfaction of a condition. The condition can be satisfied many times, so, the signal should start from the beginning each time. If I want to put it in another way: You can take step input instead of the designed signal. Step input is to be reset conditionally. How can I make it?
I haven't seen such a functionality built-in Simulink (maybe the newer versions have it?) but here is a workaround:
You can simulate passed time with an integrator that has a Constant block set to 1 as input. The point is that the integrator block has a reset port which you can connect to your condition. So, when your condition becomes true, the integrator restarts a time variable from 0 (which is set in the initial conditions). Beforehand, you need to have your signal saved in something like a Table Lookup block, which outputs the signal as a function of time. Then you connect the integrator output to the Table Lookup block.
Have you tried putting your Signal Builder block in an enabled subsystem? You probably need to set the states when enabling to reset for it to work. Have a look at Create an Enabled Subsystem in the documentation for more details.