I am trying to calculate the number of page table levels that are required to support 35 virtual address bits.
The input is giving me:
The paging unit uses 16B page descriptors and page size is 2KiB. The number of descriptors stored in a descriptor table is 128.
The correct answer that is given for the page table levels is 4.
I tried to calculate it using various methods but it doesn't work out.
I also tried this formula (virtual address space size)/(page size)
Could someone please help me?
The most generic formula is like:
total_virtual_address_bits <= bits_for_offset_in_page + levels * bits_per_page_table_index
This formula is derived from splitting a virtual address up into several fields.
You can plug your values in and see that it works:
35 <= 11 + 4 * 7
35 <= 39
You can also rearrange the formula:
total_virtual_address_bits <= bits_for_offset_in_page + levels * bits_per_page_table_index
total_virtual_address_bits - bits_for_offset_in_page <= levels * bits_per_page_table_index
levels >= (total_virtual_address_bits - bits_for_offset_in_page) / bits_per_page_table_index
You can plug your values into this formula, like:
levels >= (35 - 11) / 7
levels >= 3.4285714
And here is the confusion part. The maths doesn't quite work perfectly (3.4285714 isn't a nice integer) so it gets rounded up.
This means that the highest level table will only be partially used (more specifically, we only need 3 bits for the index into the highest level page table, so only 8 entries in that table will be used and the other 120 entries will be wasted).
Note that this "rounding up" does happen in practice. One example was 32-bit 80x86 with PAE, where the highest level page table was only 32 bytes (and the size of page tables and page size where all 4 KiB).
Related
Consider a paging system with the page table being stored in memory. The logical address space used is 32 bit and the page size is 8KB. This will result in a very large page table(s) and therefore the system uses hierarchical paging with two levels. The number of entries in the outer page table is 256.
Specify the number of bits in each of the three fields composing the logical address namely, the outer page, the inner page, and the offset.
I found some information on finding the page offset, Page offset = log2(page size in bytes), so for this case, it would be 13, but I haven't found much information on how to find the number of bits for the outer page and inner page. Can anyone shine some light on this problem for me?
Thank you.
I might not be entirely correct, but since VPN to PPN translation is one of my favorite parts from OS, I decided to share my understanding. Maybe this picture can help to understand how is virtual address translated in the physical address.
In this example page directory contains 1024 entries, so you will need 10 bits, to be able to define which entry you need. This entry contains address of the inner table. Then, as the inner page table also contains 1024 entries, once you know the address of it, similarly you still need to find the index of its entry which holds the physical page address. So next 10 bits are used for calculating that index. Finally, when the page table entry gives you the physical address of the page, offset gives the exact physical address. If this is not very clear I can go into more details.
In your case, as you have 8KB pages, as you said last 13 bits will be used to calculate the offset. If the outermost page table contains 256 entries then you will need 8 bits (log2(256)) to be able to determine the index of its entry. Then it depends on the number of the entries of the inner table. Or if the size of the entry is defined, the number of entries can be calculated from it. If we assume that left 11 bits are entirely used for the inner table, than it would have to contain 2048 entries, as based on my understanding one instance of page table fits and fills one physical page.
The lowest bits of a logical address will be used for "offset in 8192-byte page". You'd need 13 bits for that (because 1 << 13 = 8192 or because log2(8192) = 13).
The highest bits of a logical address will be used for "index into 256-entry outer page table". You'd need 8 bits for that (because 1 << 8 = 256 or because log2(2562) = 8).
If a logical address is 32 bits and the lowest 13 bits and highest 8 bits are used for other things; how many bits are left over for the index into the inner page table?
The following parameters apply to a system employing a 40-bit virtual address and
1G bytes of physical (main) memory. Word size is 64 bits (8 bytes). Addresses point
to bytes and are aligned on byte boundaries. We use the following notation for an i-bit
address: Ai-1...A2,A1,A0 where Ai-1 is the most significant bit of the address and A0
is the least significant bit of the address. The virtual address is denoted by V39-V0
and the physical address is denoted by P29-P0.
Page size: 64 K bytes
Page table: three-level page table
The virtual page number is split in 3 fields of 8 bits each.
Entries in all tables are 32 bits (4 bytes).
This is what I have found so far,
Since it is a 40 bit virtual address and the Page Size is 64kB (2^16), 16 bits are for offset and we subtract 16 from 40. The remaining 24 bits are for the Virtual Page Number (VPN). The VPN is split in 3 fields of 8 bits each. So we have a three level page table. Each table has 2^8 entries and the size of each table is 2^8 * 4 bytes = 1024 bytes.
From here how would we proceed and find the total amount of virtual memory covered by one entry of page tables at each level?
At the lowest level each entry points to a single page, so working out the amount of virtual memory is trivial, its the size of 1 page. At each of the higher level, one entry represents n entries in the lower table (2^8 in this case). So for the second level its n * amount covered by a bottom level entry, or 2^8* the size of a page. Then use the size of a second level to repeat this calculation for the third level.
I solved some question, where the page table entry size needed only 26 bits - 22 for the physical address, and 4 for dirty bits and such. However it was rounded up to 32 - because 26 is not a power of 2. Must be something simple I'm missing but why do we have to do that? Thanks!
I think here that you need to realize that the page table entry needs to accessed like any other piece of data. Typically, this means that it needs to fit into a byte or a word.
Now bytes only hold 8 bits, so that is not enough room. For many machines (and I suspect, your machine too), words are 32 bits.
Thus the page table entry is allocated 32 bits of space.
Number of entries in a page table entry and the size are two things. Obviously the size is equal to the number of entries times size of a single entry. Page table entry is there to tell you which virtual page maps to which physical page. Which means, the number of entries you need in a page table entry is, number of virtual page you have. which can be calculated by dividing the total addressable space by the size of a page. (For example, 32 bit address and a 4k page size gives us 2 to the power 20 entries), virtual part of an entry will be 20 bits. Size of a physical part entry is determined by the available physical memory. Usually the page size remain same. By this way you can calculate the bits needed for a single entry. Then you can multiply this by the number of entries and you have the total size.
A processor uses 36 bit physical addresses and 32 bit virtual addresses with a page frame size of 4 KBytes. Each page table entry size is of 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows :
bits 30 - 31 are used to index into the first level page table
bits 21 - 29 are used to index into the second level page table
bits 12 - 20 are used to index into the third level page table
bits 0 - 11 are used as offset within the page
The number of bits required for addressing the next level page table ( or page frame ) in the page table entry of the first , second and third level page tables are respectively ?
This was a question asked in GATE 2008.
My Analysis: The maximum number of page frames = (physical address size) / ( page size ) = 2^36 / 2^12 = 2^24.
Thus, 24 bits will be enough to index the page numbers in the 3rd level page table. Now we have to find out how many page tables will be there in the 3rd level. Its given that 9 bits are used to index into the 3rd level page tables. So there are 2^9 page tables in level 3. That means 2^32 virtual space is contained in 2^9 page tables so entries per page table= 2^32/2^9 = 2^23. So 23 bits are required in an l2 page table entry to index the entries of a particular page table in 3rd level page table. 2^9 page tables are there in L2 from L1 page table we need to get to any one of these 2^9 page tables. So 9 bits are required in L1.
This analysis somehow doesn't seem right. I am very much confused. Can someone please explain the concepts ?
At first we have physical address of 2^36, and page size is 2^12. Hence 2^24 should be the number of pages. and you figured that right.
Since given 9 bits for 3rd level page table, ie 2^9 and then 4 bytes per entry, so 2^11. Now 2^36/2^11 would give 2^25. Hence 25 bits (25 bits at second level table).
Now again given 9 bits for second level page table. so the same logic applies again
2^36/2^11, which again is 2^25.(25 bits at first level table).
hence the answer must be
25,25,24
One thing that you have to understand is, that though virtual address space is 2^32, we need to map the entire 2^36 entries and not 2^32.Also, each page can take care of 2^9 * 2^2, and you didn't consider this 2^2 as well. The same thing holds at the higher level as well
You should have a look at this question
and this wikipedia entry, especially the figure.
In this question, there are 36 bits of physical memory, out of which 12 bits are designated for the offset. The offset is not going to change in any level (since it is the size of the page). Therefore in any level there will be 24 frame bits required for the page table. Since there are 36 bits of physical memory, you cannot increase the physical memory size by increasing the number of bits in the page table.
Example question from a past operating system final, how do I calculate this kind of question?
A computer has a 64-bit virtual address space and 2048-byte pages. A page table entry takes 4 bytes. A multi-level page table is used because each table must be contained within a page. How many levels are required?
How would I calculate this?
Since page table must fit in a page, page table size is 2048 bytes and each entry is 4 bytes thus a table holds 2048/4=512 entries. To address 512 entries it requires log2(512)=9 bits. The total number of bits available to encode the entry for each page level is 64-log2(2048)=53 bits (the number of bits of address space minus the page offset bits). Thus the total number of levels required is 53/9=6 (rounded up).
The x86-64 default page table size is 4096 bytes, each page table must fit in a page and a page table entry is 8 bytes. Current CPUs only implement 48 bits of virtual address space. How many page table levels are required?
Logical Address bit=64,
Number of page will be= 2^64/2048 = 2^64/2^11 = 2^53
Pages we have entry sine of page table= 4 Byte ,
Number of Entry in 1 Page will be= 2048/4=>512,
bit To represent one Entry=Log(512)=9bit,
and bit for Page is= 53bit
Therefore Number of Level =53/9=>6 Level Page Table