Can I use wires from top module as inputs in a bind module instantiation? (SystemVerilog) - system-verilog

Question

I have a simple module PRINTER that I want to instantiate with bind to another module BIG_DUT in one testbench BIG_TB. BIG_DUT has an instance of another module SMALL_DUT, which has most stuff that I want to use in PRINTER. I have another testbench SMALL_TB which has an instance of SMALL_DUT as well as an instance of PRINTER, and in this testbench I would like to bind the PRINTER to the SMALL_DUT.
In my PRINTER module I need a wire that is present in either testbench, as well as in BIG_DUT, but not in SMALL_DUT. Is there any way to use the wire from the testbench instead of trying to access the wire inside of BIG_DUT/SMALL_DUT, while still having easy access to other wires/stuff in SMALL_DUT?
Example code:
module SMALL_DUT();
// Stuff I want to use in the PRINTER
...
endmodule
module BIG_DUT(
input wire big_dut_input
);
SMALL_DUT small_dut_in_big();
endmodule
module PRINTER(
// Can I take input here from tb?
);
// For BIG_TB, I could use big_dut_input and small_dut_in_big.stuff_i_want_to_use
// For SMALL_TB, there is no wire I could use, but I can reference stuff_i_want_to_use
endmodule
module BIG_TB();
wire my_tb_wire_big; // Want to use this in PRINTER, also present in BIG_DUT
BIG_DUT big_dut(
.big_dut_input(my_tb_wire_big)
);
// I could potentially do
// bind big_dut.small_dut_in_big
// here to get the same access pattern to stuff inside PRINTER
bind big_dut
PRINTER big_printer(
// Could I input my_tb_wire_big here?
);
endmodule
module SMALL_TB();
wire my_tb_wire_small; // Same usage as my_tb_wire_big in PRINTER
...
SMALL_DUT small_dut();
bind small_dut
PRINTER small_printer(
// Could I input my_tb_wire_small here?
);
endmodule
(In this simple example I could of course add another input to SMALL_DUT, but that is used in my real code, and I don't want the extra input there.)

Answer 1

You can always put a hierarchical reference in an instance port connection. This is true regardless of using the bind construct or not.
module SMALL_DUT();
bit stuff;
...
endmodule
module BIG_DUT(
input wire big_dut_input
);
SMALL_DUT small_dut_in_big();
endmodule
module PRINTER(
input signal1, signal2, signal3)
// stuff
endmodule
module BIG_TB();
wire my_tb_wire_big; // Want to use this in PRINTER, also present in BIG_DUT
BIG_DUT big_dut(
.big_dut_input(my_tb_wire_big)
);
bind big_dut
PRINTER big_printer(
BIG_TB.my_tb_wire_big, small_dut_in_big.stuff);
);
endmodule
module SMALL_TB();
wire my_tb_wire_small; // Same usage as my_tb_wire_big in PRINTER
...
SMALL_DUT small_dut();
bind small_dut
PRINTER small_printer(
SMALL_TB.my_tb_wire_small, stuff
);
endmodule