How to resolve design.sv:1 : syntax error on the EDA playground for the sillyfunction taken from Digital Design And Computer Architecture? - system-verilog

Question

For understanding SystemVerilog, I have been writing the codes on the Digital Design And the Computer Architecture. So, I wrote the first example and the testbench in the book.
Design
module sillyfunction(input logic a,b,c,
output logic y);
assign y = ~a & ~b & ~c |
a & ~b & ~c |
a & ~b & c;
endmodule
Testbench
module testbench();
input a, b, c;
output y;
sillyfunction dut(a,b,c,y);
initial begin
$dumpfile("file.vcd");
$dumpvars(1);
a = 0; b = 0; c = 0;
#10
c = 1;
#10
b = 1; c = 0;
#10
c = 1;
#10
a = 1; b = 0; c = 0;
#10
c = 1;
#10
b = 1; c = 0;
#10
c = 1;
end
endmodule
The problem is I have encountered the error:
[2021-10-30 14:44:15 EDT] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out
design.sv:1: syntax error
I give up.
Exit code expected: 0, received: 1
Done
I tried to debug it with the changing the input and output variables to reg and wire which has no effect. I also tried to
$dumpvars(1) to $dumvars(0)
Which has no effects on the bug.
How can I resolve the bug?

Answer 1

I also see that error when I run your code on an old version of iverilog on edaplayground. I suspect the version you used only supports the old Verilog standard, but does not have much support for SystemVerilog features; hence, the vague syntax error message. It probably did not recognize the logic keyword, which is specific to SystemVerilog.
You should switch to the latest version there (Icarus Verilog 0.10.0), which has better SystemVerilog support. You will get a different message, but I didn't find that to be very helpful either.
But, switching to another simulator, like Cadence, produces a more helpful message:
input a, b, c;
|
xmvlog: *E,NOPORT (testbench.sv,10|8): input/output/inout 'a' not declared in port list [12.3.2(IEEE)].
Here is the link: edaplayground.
Typically, you don't need ports on a testbench since it is usually the top-level module. Using reg and wire, as you mentioned is one way to fix the error. Another way is to change:
input a, b, c;
output y;
to:
logic a, b, c;
logic y;

Answer 2

Icarus Verilog (aka iverilog) version 0.9.* do not support SysmteVerilog. Version 0.10.* does support a limited subset of SystemVerilog features with the compiler flag -g2012. Note the Compile Options in the image from EDA playground
In your testbench, change:
input a, b, c;
output y;
to:
logic a, b, c; // could also be 'reg' type
wire y; // could also be 'logic' type

Answer 3

The problem seems to be with the port declaration style you have followed for the module testbench.
This is a non-ANSI port declaration style and System-verilog discusses on this under the LRM standard section, 23.2.2.1 Non-ANSI style port declarations. To get this working, you will have to change
module testbench(); -> module testbench(a,b,c,y);
Next, ports a,b,c and y are wires. A wire cannot be assigned like "a = 1;". So you can change a wire to a variable by :
input a, b, c; output y; -> input var a, b, c; output var y;