randcase weight behaviour unexpected - system-verilog

Question

class test1;
function test_randcase();
for (int idx=0; idx < 10; idx++) begin
randcase
50: begin
$display("displaying from first cases");
end
50: begin
$display("displaying from second case");
end
endcase
end
endfunction
endclass
program main;
initial begin
test1 t1=new();
t1.test_randcase();
end
endprogram
Since each case is equally weighed here (50/100=0.5) so the expectation is that I would see each display 5 times in total. However, I see "first case" print 6 times and "second case" print 4 times. If this is the behavior of randcase, then how would I achieve my intention of equal weight? I used vcs compiler for this execution.
output:
displaying from second case
displaying from first cases
displaying from first cases
displaying from first cases
displaying from first cases
displaying from second case
displaying from first cases
displaying from second case
displaying from second case
displaying from first cases

Answer 1

Looking at this problem another way, suppose you had to choose a completely random 10-bit number where each bit has a 50% chance of being 0 or 1. There are 1024 possible numbers with a 1/1024 chance of having 10 1's and a 1/1024 chance of having 10 0's. And the odds of choosing a number with exactly 5 1's and 5 0's is around 25%. If you run more iterations, your randcase distribution would approach 0.50, but the odds of getting an exact 0.5 distribution diminish.
If your requirement is getting an exact distribution, you need to know upfront how many iterations you plan to have. There are several approaches you could take, one of which I can show you
class test1;
enum {FIRST, SECOND} itor[10];
function new;
itor[0:4] = '{5{FIRST}};
itor[5:9] = '{5{SECOND}};
endfunction
function void test_randcase();
itor.shuffle();
foreach(itor[i]) begin
case(itor[i])
FIRST: begin
$display("displaying from first cases");
end
SECOND: begin
$display("displaying from second case");
end
endcase
end
endfunction
endclass
module main;
test1 t1=new();
initial repeat(10)begin
$display("---");
t1.test_randcase();
end
endmodule
Other ways are shown in my paper from DVCon 2020, SystemVerilog Constraints: Appreciating What You Forgot in School to Get Better Results