Is There A Technical Reason SystemVerilog Cannot Pass Module Name as Parameter? - system-verilog

Question

I want to do something like this:
module BusinessLogicVersion_1(clk, rst, d, q);
// Erudite business logic goes here
endmodule
module BusinessLogicVersion_2(clk, rst, d, q);
// Different implementation of same interface.
endmodule
// Then, when instantiating the module that requires an implementation of whatever interface,
// I want to do something like this:
ModuleXyz #(
.business_logic(BusinessLogicVersion_2) // <--- Pass an implementation of an interface as parameter
) (.clk(clk), .rst(rst), ...);
I have tried to find ways to do this, and from what I've read SV does not allow it.
My question is:
Is there a technical reason why this shouldn't be possible?

Answer 1

Technically, nothing is technically impossible in software given enough time, space and money! StackOverflow is not the forum for why kinds of questions.
SystemVerilog has a different approaches that implements what you are looking for. One way is called a configuration (See section 33. Configuring the contents of a design in the IEEE 1800-2017 SystemVerilog LRM).
For your case, what you would do is compile different versions of same module name ModuleXyz into different libraries and then use either command line options or a config block that selects which version to be selected for different instances. I would look at the LRM for examples.
The other method is using a _generate construct to select different modules you want instantiated. See section 27. Generate constructs. This is simpler, but less flexible since you have to know upfront which versions are available.
case(VERSION):
1: BusinessLogicVersion_1 inst (clk, rst, d, q);
2: BusinessLogicVersion_2 inst (clk, rst, d, q);
default: $error("Version does not exist");
endcase

Answer 2

I assume you're trying to do some kind of dependency injection, where the modules you're passing in are supposed to be different strategies. Also, I see from your profile that you're familiar with C++, so I'll try to map what you're trying to do onto that language. (Beware of gross simplifications or not-so-accurate analogies.)
A SystemVerilog module is akin to a C++ class. By passing a module name to you ModuleXyz, you're trying to do something like pass a class as a function argument in C++. This isn't possible in that language either. You generally pass instances of classes.
In order to pass an instance of a class, you'd need to first construct it. This would mean passing it your desired constructor arguments. Your module has ports, which are conceptually similar to a class's constructor arguments. When you instantiate a module, you connect its ports.
In your example, I'm guessing you would like to pass in the type of module that ModuleXyz should instantiate inside. In C++ you would generally pass a factory object, which knows how to construct the object you need, with the constructor arguments you want. This pattern isn't possible with modules, as only "direct" instantiation is allowed.
As #dave_59 pointed out, switching out module types is done using configurations. It's sort of like doing dynamic loading of different shared libraries, to switch out the implementations.
If your simulator doesn't support configurations (as language constructs), it will usually provide compile switches that allow you to implement something similar. It will compile different versions of the module, but you will be able to choose which one gets "linked".
If you really, really need to use dependency injection, I'd suggest you try to migrate your code from trying to pass modules, to passing interfaces. It is possible to pass instances of those around. Just remember, that you'll be passing already constructed instances, not types.