I'm trying to simulate a SMPM with a VoltageController and a PWM in OpenModelica. After looking for old threads on the subject I found this one: PI-Controller doesn't reach reference value with inverter and PMSM in Modelica
Basically, that's exactly what I'm looking for. However, after copying #marco 's code and pasting it into Modelica, I have an error as seen in the attached image.
The PWM block is not displayed here. and the VoltageToDutyCycle block is missing a connection.
Can someone help me what's going on there, or even send me an executable version?
Maybe I'm doing something wrong, since I'm still a beginner at Modelica I don't want to rule that out ;)
I corrected the answer, it should work now.
Keep in mind, that this code was written with Modelica Standard Library (MSL) 3.2.3. The current version is 4.0.0. Either use the old MSL or
convert to the new version.
The missing MySignalPWM block was just the original block from the MSL. The class path is fixed now.
Regarding the connection: there is nothing missing. The third boolean input is disabled, but OpenModelica still displays it. Other Modelica tools are smarter and do not show disabled connectors. The thermal port in the center of this component should also not be visible.
Related
I have some test simulations that, when run, do not follow the exact same solution path when run in Dymola 2021x and Dymola 2022. Thus, my system that checks to make sure my test simulations are running properly indicates that they are in fact not running properly. It appears that the simulations are still within +/-2*tolerance of each other. I am attempting to learn why it would be that the solutions are not numerically identical if they inputs and models are identical. Nothing in the update release indicated that there were any solution method changes.
From the Dymola 2022 Release Notes, one possible explanation could be in the different Modelica Language Specifications (3.4 in Dymola 2021x, 3.5 in Dymola 2022), either affecting the models directly (MSL 4.0.0 is compliant with the Language Specification 3.4, for example), or the way the models are handled during translation.
You mention you have a system in place that checks your simulation. Is it implemented in Modelica, that is, might it be affected by the different Language Specifications?
Personally, I tend to expect in each release minor changes/improvements in the translation algorithms and in the solvers; even though they might not be mentioned in the release notes. Perhaps this attitude only works because my models are rather coarse, so I cannot really say whether such a change in the computed solution (+-2*tolerance, tolerance=0.1% in my case) is bringing me closer or farther away from the real solution.
I have been exploring Open Modelica for a week for system Dynamics. All though I learned few basic things(like function and class syntax etc..) from Spoken Tutorial, I need to go a long way. I am not to find a proper source mentioning the syntaxes for various aspects. For example, I am not able to find syntax for writing derivatives(dy/dx) apart from the time derivative[ der(x)]. Is there someplace where I can look into for further proceeding?
P.s. I am new to Softwares like MATLAB, Octave etc.. and OpenModelica is my first one.
OpenModelica is a Modelica tool. All Modelica related resources, e.g. language specification, can be found here: https://www.modelica.org/
I implemented a (medium to big) simulink model in v2012b.
I thought it would work also in 2010bSP2, but it didn't. Some mask blocks are not opening and other strange errors.
In previous versions of simulink there was a "save as simulink 201x" model to force compatibility, but I couldn't find it anymore in 2012b.
Any clues on how to avoid rework?
Starting with 2012b, and the new interface, they have moved the option to the menu:
File / Export Model to / Previous Version
The feature never seems to fully work, and I often get warnings when first loading a model into an older version, so I would recommend giving your model a thorough check over and test. I always save again from the correct version, to clear the warnings.
The refactoring for a New Simulink Version can show up at several points.
Your own libraries: There is a feature called "Forwarding Tables" that allows you to specify where a block in the new library is (I suppose you will have to refactor your libraries as well, and probably someone else uses those libraries too)
It sounds like a biiig hack (and it is) but i found it sometimes the path of lowest resistantce... Just open your model in the Editor of your choice and replace the block paths whith the common refactoring funcitons. It is terrible i know but Simulink really lacks of refactoring functions...
I'm looking for a tool to convert a SBML model into a Matlab function. I've tried SBMLTranslate() function from libSBML but this returns a Matlab struct, not a function. Does anybody know if such tool exists? Thanks
There are at least three efforts in this direction:
Frank Bergmann offers an online service for SBML translation where you can upload an SBML file and it will generate a MATLAB file. The comments at the top of the generated MATLAB file explain how to use the results. The C++ source code is available on SourceForge.
Bergmann's code referenced above was used by Stanley Gu to create sbml2matlab, a Windows standalone program. Off-hand, I don't know whether Gu's version changed or enhanced the algorithm used by the Bergmann version, but it seems likely. (Note: Gu now works at Google and does not maintain this code anymore, as far as I know.)
The Systems Biology Format Converter (SBFC) is a framework written principally by Nicolas Rodriguez; it includes a collection of converters, one of which is an SBML-to-MATLAB converter. This converter is written in Java.
I have not compared the results of the translators myself yet, so cannot speak to the differences or quality of output. If you try them and have any feedback to relate, please let the authors know. Knowing what has or hasn't worked for real users will help improve things in the future.
A final caveat is that all of these have been research projects, so make sure to set your expectations accordingly. (This is not a criticism of the authors; the authors are very good – I know most of them personally – but the reality of academic development work is that we all lack the time and resources to make these systems comprehensive, hardened, polished, and documented to the degree that we wish we could.)
A friend of mine needs to implement some statistical calculations in hardware.
She wants it to be accomplished using VHDL.
(cross my heart, I haven't written a line of code in VHDL and know nothing about its subtleties)
In particular, she needs a direct analogue of MATLAB's betainc function.
Is there a good package around for doing this?
Any hints on the implementation are also highly appreciated.
If it's not a good idea at all, please tell me about it as well.
Thanks a lot!
There isn't a core available that performs an incomplete beta function in the Xilinx toolset. I can't speak for the other toolsets available, although I would doubt that there is such a thing.
What Xilinx does offer is a set of signal processing blocks, like multipliers, adders and RAM Blocks (amongst other things, filters, FFTs), that can be used together to implement various custom signal transforms.
In order for this to be done, there needs to be a complete understanding of the inner workings of the transform to be applied.
A good first step is to implement the function "manually" in matlab as a proof of concept:
Instead of using the built-in function in matlab, your friend can try to implement the function just using fundamental operators like multipliers and adders.
The results can be compared with those produced by the built-in function for verification.
The concept can then be moved to VHDL using the building blocks that are provided.
Doing this for the incomplete beta function isn't something for the faint-hearted, but it can be done.
As far as I know there is no tool which allow interface of VHDL and matlab.
But interface of VHDL and C is fairly easy, so if you can implement your code(MATLAB's betainc function) in C then it can be done easily with FLI(foreign language interface).
If you are using modelsim below link can be helpful.
link
First of all a word of warning, if you haven't done any VHDL/FPGA work before, this is probably not the best place to start. With VHDL (and other HDL languages) you are basically describing hardware, rather than a sequential line of commands to execute on a processor (as you are with C/C++, etc.). You thus need a completely different skill- and mind-set when doing FPGA-development. Just because something can be written in VHDL, it doesn't mean that it actually can work in an FPGA chip (that it is synthesizable).
With that said, Xilinx (one of the major manufacturers of FPGA chips and development tools) does provide the System Generator package, which interfaces with Matlab and can automatically generate code for FPGA chips from this. I haven't used it myself, so I'm not at all sure if it's usable in your friend's case - but it's probably a good place to start.
The System Generator User guide (link is on the previously linked page) also provides a short introduction to FPGA chips in general, and in the context of using it with Matlab.
You COULD write it yourself. However, the incomplete beta function is an integral. For many values of the parameters (as long as both are greater than 1) it is fairly well behaved. However, when either parameter is less than 1, a singularity arises at an endpoint, making the problem a bit nasty. The point is, don't write it yourself unless you have a solid background in numerical analysis.
Anyway, there are surely many versions in C available. Netlib must have something, or look in Numerical Recipes. Or compile it from MATLAB. Then link it in as nav_jan suggests.
As an alternative to VHDL, you could use MyHDL to write and test your beta function - that can produce synthesisable (ie. can go into an FPGA chip) VHDL (or Verilog as you wish) out of the back end.
MyHDL is an extra set of modules on top of Python which allow hardware to be modelled, verified and generated. Python will be a much more familiar environment to write validation code in than VHDL (which is missing many of the abstract data types you might take for granted in a programming language).
The code under test will still have to be written with a "hardware mindset", but that is usually a smaller piece of code than the test environment, so in some ways less hassle than figuring out how to work around the verification limitations of VHDL.