If there were no enable signal, inputReady ##N outputValid would do the job. But, how should I exclude the cycles when enable is deasserted? Is there a short solution?
If you want to include only the portion when enable is asserted, you can just use a repetition operation. For example, if N == 4:
inputReady ##0 enable [*4] ##1 enable && outputValid;
// or
inputReady ##0 enable [*5] ##0 outputValid;
// or
inputReady && enable ##1 enable [*3] ##1 enable && outputValid;
The repetition is equivalent to N-1 delays:
enable ##1 enable ##1 enable ##1 enable
If you're building an assertion to check if-this-then-that, you could use the simple form:
inputReady |-> enable [*5] ##0 outputValid;
These are all equivalent:
inputReady |-> enable [*4] ##1 enable && outputValid;
inputReady && enable |=> enable [*4] ##0 outputValid;
inputReady && enable |=> enable ##1 enable ##1 enable ##1 enable && outputValid;
Related
I have to write a single SVA for the complete protocol shown in this image
I wrote the following SVA but it doesn't capture the immediate ack. How do I fix that
#(posedge clk)
$rose(val) |=>
( $stable(data) && !ack && val ) ##[1:64] ( ack && val ) ##1 ( !ack && !val )
Looking at your assertion, it won't capture the immediate ACK because you are expecting a sequence excluding an immediate ACK with !ack. I would re-write your assertion as:
sequence seq;
$stable({address, data}) ##[0:63] (val && ack && $stable({address, data})) ##1 !ack ##1 !val;
endsequence
property p;
#(posedge clk)
$rose(val) |=> seq;
endproperty
as_protocol : assert property(p);
Im writing assertions for a handshake protocol where there can be back to back requests and acks. Acks can come between 1 to 5 cycles after req. How can I use assertions to make sure there is 1 ack for every req while also taking glitching on req or ack into account ?
property p1:
#(posedge clk) req ##[1:5] ack ;
endproperty
property p2:
#(posedge clk) $rose(ack) |-> $past(req,5);
Im not sure if this keeps 1-to-1 mapping of req vs ack.
Can there be two requests before an ack? If not I would write :
property p_test;
#(posedge clk)
$rose(req) |=> !req[*0:$] ##0 ack;
endproperty
It works if req is pulse only
Property2 below is not in sync with property 1.
property p2: #(posedge clk) $rose(ack) |-> $past(req,5);
You are saying that ack must have had a request 5 clocks earlier. But property 1 says that req followed by ack is valid.
I think you need a id with a request that you can match when the ack happens.
sequence s_ack_check;
byte id;
(req && id == ack_id) ##[1:5](ack && ack_id == id);
endsequence
I take it you meant that there could be multiple reqs before any acks? If so, the solution needs either property variables or helper logic. Formal properties don't have memory or counters (without using variables).
Here's some code if you want to use helper logic:
Assume you allow at most 15 outstanding and it takes at most 25 clocks to get all acks:
logic [3:0] req_cnt, ack_cnt;
always # (posedge clk) if (rst) req_cnt <= 0; else req_cnt <= req_cnt + req;
always # (posedge clk) if (rst) ack_cnt <= 0; else ack_cnt <= ack_cnt + ack;
assert property (# (posedge clk) disable iff (rst) sync_accept_on(req) ##25 req_cnt == ack_cnt);
Count the requests and acks. Then assert that after 25 cycles of no req, the req_cnt == ack_cnt.
If there's never more than 1 req outstanding, the logic is much simpler. Please clarify if that is the case.
I am trying to write a property with a case statement, straight out of the SystemVerilog 2012 LRM.
property p_rate_select (logic [1:0] rate);
case (rate)
2'd0 : $rose(i_ffs_rdcount == 1) |=> $fell(o_telem_fifo_ready_n);
2'd1 : $rose(i_ffs_rdcount == 2) |=> $fell(o_telem_fifo_ready_n);
2'd2 : $rose(i_ffs_rdcount == 3) |=> $fell(o_telem_fifo_ready_n);
2'd3 : $rose(i_ffs_rdcount == 4) |=> $fell(o_telem_fifo_ready_n);
default : 0;
endcase
endproperty
Using QuestaSim 10.4B, I get the following error:
** Error: (vlog-13069) checker.sv(196):
near "case": syntax error, unexpected case, expecting disable.
Is case statements not supported with this version of Questasim?
You need Questa 10.4e or newer.
I want assertion that if in current cycle signal 'a' equal to "0110"(in binary) in the next cycle signal'b'not bigger than 31(it should be between 0 and 31.it should be less than 00000000000000000000000000011111)(its width equal 32)
Can everyone help me to write assertion?!
Excuse me for my bad english.
assert property ( # (posedge clk ) (a == 32'b0110) |=> ( b > 32'd0 && b < 32'd32 ) );
assert - will set the property( assertion ) into action. The property has to be based on a clock . Choose the appropriate clock which is triggering the registers a & b in the design. Implication operator |=> indicates that the property has to be true in the next clock cycle. In this case if a equals 6, the next cycle b has to between 0 and 32 ).
In case of a failure some similar message ( based on the simulator ) will be displayed.
top.unnamed$$_0: started at ns failed at ns
Offending '((b > 0) && (b < 32))'
You can read up a basic tutorial on assertions
https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/
property clk_req_check;
#(posedge upbm_clk) disable iff (~upbm_reset_n)
//#(posedge upbm_clk);
case (sb_adrc)
2'b00 : 1'b1 |-> (clk_req[0] == 1'b1) [*] (sb_adrc != 2'b00);
2'b01 : 1'b1 |-> (clk_req[1] == 1'b1) [*] (sb_adrc != 2'b01);
2'b10 : 1'b1 |-> (clk_req[2] == 1'b1) [*] (sb_adrc != 2'b10);
2'b11 : 1'b1 |-> (clk_req[3] == 1'b1) [*] (sb_adrc != 2'b11);
default : 1'b0;
endcase
endproperty: clk_req_check
** Error: (vlog-13069) cad_property.sv(5): near "case": syntax error, unexpected case.
without disable_iff
** Error: (vlog-13069) cad_property.sv(3): near "case": syntax error, unexpected case, expecting disable.
case/endcase within an assertion may not supported in your version of Questa.
That's interesting, I've never tried writing a case statement inside a concurrent assertion, not sure if that is allowed. Thinking about it though, you want to simultaneously be checking all 4 values of sb_adrc with concurrent assertions (which run constantly on every upbm_clk), which feels to me that you need 4 separate concurrent assertions. Each one similar to the following:
property clk_req_check;
#(posedge upbm_clk) disable iff (~upbm_reset_n)
sb_adrc == 2'b00 |-> (clk_req[0] == 1'b1) ##1 (sb_adrc != 2'b00)
endproperty