Assignment operator type check failed on interface parameters - system-verilog

Question

I'm working on parameterizing my interface to support multiple different instances:
compilation is failing on type mismatch:
assignment operator type check failed on instance hw_top (expecting
datatype compatible with 'virtual interface
foo_if#(.BASE_ADDR_1(32'h0000f480),.SIZE_1(32'h00000014),.BASE_ADDR_2(32'h00000000),.SIZE_2(32'h00000000))'
but found an incompatible
'foo_if#(.BASE_ADDR_1(32'h00002a00),.SIZE_1(32'h00000008),.BASE_ADDR_2(32'h00002a10),.SIZE_2(32'h00000008))
instance' instead).
This is how my interface is defined:
interface foo_if #(
parameter BASE_ADDR_1 = 'hf480,
parameter SIZE_1 = 'h14,
parameter BASE_ADDR_2 = 'h0,
parameter SIZE_2 = 'h0
)(
input clk,
input rst_n
);
//some logic
endinterface
This is how I instantiate it:
interface harness_if(
(
foo_if#(
.BASE_ADDR_1('h2a00),
.SIZE_1('h8),
.BASE_ADDR_2('h2a10),
.SIZE_2('h8)
) foo_if_i (
.clk (axi2af_clk),
.rst_n (resetn)
);
endinterface harness_if//
and I bind the harness if like this: harness_if
bind hw_top harness_if harness_i();
The whole idea of the parameter is that I can assign it to different values, so I'm unsure what is wrong.

Answer 1

The problem is that you are trying to place an instance of your interface where the port list of another interface should be. That is illegal syntax.
You want to place the interface instance inside the body of a module.
Here is a complete code example which shows 2 instances of your interface which use different parameter values:
interface foo_if #(
parameter BASE_ADDR_1 = 'hf480,
parameter SIZE_1 = 'h14,
parameter BASE_ADDR_2 = 'h0,
parameter SIZE_2 = 'h0
)(
input clk,
input rst_n
);
endinterface
module tb;
bit axi2af_clk, resetn;
foo_if # (
.BASE_ADDR_1('h2a00),
.SIZE_1 ('h8),
.BASE_ADDR_2('h2a10),
.SIZE_2 ('h8)
) foo_if_i (
.clk (axi2af_clk),
.rst_n (resetn)
);
foo_if # (
.BASE_ADDR_1('h1000),
.SIZE_1 (16),
.BASE_ADDR_2('h1010),
.SIZE_2 (16)
) foo_if_2 (
.clk (axi2af_clk),
.rst_n (resetn)
);
endmodule