how does phase mechanism works in UVM? - system-verilog

Question

I'm trying to understand UVM phasing mechanism especially in connect_phase().
UVM_INFO testbench.sv(14) # 0: e2.c1.gc1 [connect] phase
UVM_INFO testbench.sv(14) # 0: e2.c1.gc2 [connect] phase
UVM_INFO testbench.sv(39) # 0: e2.c1 [connect] phase
UVM_INFO testbench.sv(14) # 0: e2.c2.gc1 [connect] phase
UVM_INFO testbench.sv(14) # 0: e2.c2.gc2 [connect] phase
UVM_INFO testbench.sv(39) # 0: e2.c2 [connect] phase
UVM_INFO testbench.sv(62) # 0: e2 [connect] phase
Not like build phase, in connect_phase, the connect phase executed from bottom-up.
Someone says that it's not the matter after build_phase() done. But in hte every single simulation, I can see the bottom-up way.
I think there is some special or inevitable reason to do that, would you please help me for understand Why a connect phase and else phase in a UVM execute from bottom-up except build and finish phase?

Answer 1

Technically the build_phase is a breadth-first ordering. The ordering of the build_phase is dictated by the fact that the parent's build_phase creates its children, so naturally the parent must execute its phase before the children's phase.
You should only concern yourself with the ordering between phases, not ordering between components within the same phase. The connect_phase only requires that the components you are connecting have been constructed first and does not care about the order you make connections.
You might want to read this discussion about phase ordering with an attached example for more details.