The Multiple Driver error in system verilog - system-verilog

Question

I was creating a code for the i2c slave. I am using a counter to change state, however I am encountering the error. The state machine that I was creating is for the single write and single read cycle.
I2C Protocol Image
Multiple drivers to always_ff output variable data_counter detected.
2 input logic i2c_slave_sda_i, //to the master
3 input logic i2c_slave_scl, //to the master
4 input logic i2c_slave_rstn, //to the master
5 output logic i2c_slave_sda_o,
6 output logic i2c_slave_sda_oe,
7 output logic i2c_slave_rd_addr, //to the register file
8 output logic i2c_slave_wr_stb, //to the register file
9 output logic i2c_slave_wr_addr, //to the register file
10 output logic i2c_slave_wr_data, //to the register file
11 input logic i2c_slave_read_data);//from the register file
12
13 logic start_detect, stop_detect;
14 logic start_resetter, stop_resetter;
15 logic read_write_bit = 0; //the write or read operation 0=write and 1=read
16 logic send_ack;
17 logic reset_counter;
18 logic data_read_out;
19 logic data_write_out;
20 logic [7:0] data_in;
21 logic [7:0] data_read;
22 logic [6:0] regaddr, addr;
23 logic [6:0] address_counter; //used as counter to count the bits of slave address transferred
24 logic [7:0] data_counter; //used as counter to count the bits of data transferred
25 //as it becomes 0, it enters into the next state
26
27 parameter [6:0] slave_address = 7'b1100000;
28
29
30 typedef enum logic [4:0] {IDLE,
31 SLAVE_ADDR,
32 WRITE,
33 REGADDR,
34 WRITE_DATA,
35 SLAVE_ADDR_READ,
36 READ,
37 READ_DATA} state_t;
38 state_t curr_state, next_state;
39
40
41 //State Machine//
42 always_ff #(posedge i2c_slave_scl or negedge i2c_slave_rstn) begin
43 if (!i2c_slave_rstn) begin
44 curr_state <= IDLE;
45 end
46 else begin
47 curr_state <= next_state;
48 end
49 end
50
51 always_comb begin
52 address_counter = 0; //count is zero for preparation of counting the bits of slave address and the data
53 data_counter = 0;
54
55 case(curr_state)
56
57 IDLE: begin
58 if (start_detect) begin
59 next_state = SLAVE_ADDR; //if start condition was detected, the state will proceed to matching the slave address
60 end
61 else begin
62 next_state = IDLE; //if start condition was not detected, the SDA remains IDLE
63 end
64 end
65
66 SLAVE_ADDR: begin
67 if (address_counter == 6) begin
68 next_state = WRITE;
69 end
70 else begin
71 next_state = IDLE; //if the slave_address don't match, the SDA will return to IDLE
72 end
73 end
74
75 WRITE: begin
76 if (read_write_bit) begin
77 send_ack = (address_counter == 9) ? 0 : 1;
78 next_state = REGADDR; //if the slave_address match and the operation is write
79 reset_counter = 0;
80 end
81 else begin
82 next_state = IDLE;
83 end
84 end
85
86 REGADDR: begin
87 if (data_counter == 7) begin
88 send_ack = (data_counter == 9) ? 0 : 1;
89 next_state = WRITE_DATA;
90 reset_counter = 0;
91 end
92 else begin
93 next_state = REGADDR;
94 end
95 end
96
97 WRITE_DATA: begin
98 if(i2c_slave_sda_i == data_in) begin
99 send_ack = (data_counter == 9) ? 0 : 1;
100 next_state = IDLE;
101 end
102 else if (start_detect) begin
103 next_state = SLAVE_ADDR_READ;
104 end
105 end
106
107 SLAVE_ADDR_READ: begin
108 if (address_counter == 6) begin
109 send_ack = (address_counter == 9) ? 0 : 1;
110 next_state = READ_DATA;
111 reset_counter = 0;
112 end
113 else begin
114 next_state = IDLE; //if the slave_address don't match, the SDA will return to IDLE
115 end
116 end
117
118 READ: begin
119 if (!read_write_bit) begin
120 send_ack = (data_counter == 9) ? 0 : 1; //if the slave_address match and the operation is read
121 next_state = READ_DATA;
122 end
123 else begin
124 next_state = IDLE;
125 end
126 end
127
128 READ_DATA: begin
129 if (i2c_slave_sda_i == data_read) begin
130 send_ack = (data_counter == 9) ? 0 : 1;
131 next_state = IDLE;
132 end
133 else begin
134 next_state = READ_DATA;
135 end
136 end
137
138 default: begin
139 next_state = IDLE;
140 end
141 endcase
142 end
143
144 //Start Condition
145 always_ff # (negedge i2c_slave_sda_i) begin
146 if (!i2c_slave_rstn) begin
147 start_detect <= 1'b1;
148 end
149 end
150
151 always_ff # (negedge i2c_slave_scl or negedge i2c_slave_rstn) begin
152 if (!i2c_slave_rstn) begin
153 start_resetter <= start_detect;
154 end
155 else begin
156 start_resetter <= i2c_slave_scl;
157 end
158 end
159
160 //Stop Condition
161 always_ff # (posedge i2c_slave_sda_i) begin
162 if (!i2c_slave_rstn) begin
163 stop_detect <= 1'b1;
164 end
165 end
166
167
168 //Matching of the slave address
169 always_ff #(posedge i2c_slave_scl or negedge i2c_slave_rstn) begin
170 if (!i2c_slave_rstn) begin
171 address_counter <= '0; //count is zero for preparation of counting the bits of slave address
172 end
173 else if (address_counter == 0) begin
174 addr[address_counter] <= i2c_slave_sda_i;
175 address_counter <= address_counter + 1;
176 end
177 end
178
179 //Storing the register address
180 always_ff #(posedge i2c_slave_scl or negedge i2c_slave_rstn) begin
181 if (!i2c_slave_rstn) begin
182 data_counter <= '0;
183 end
184 else if (data_counter == 0) begin
185 regaddr[data_counter] <= i2c_slave_sda_i;
186 data_counter <= data_counter + 1;
187 end
188 end
189
190 //Storing the Data byte at write cycle
191 always_ff #(posedge i2c_slave_scl or negedge i2c_slave_rstn) begin
192 if (!i2c_slave_rstn) begin
193 data_in <= 8'b00000000;
194 end
195 else begin
196 data_in [7] <= i2c_slave_sda_i;
197 data_in [6] <= data_in [7];
198 data_in [5] <= data_in [6];
199 data_in [4] <= data_in [5];
200 data_in [3] <= data_in [4];
201 data_in [2] <= data_in [3];
202 data_in [1] <= data_in [2];
203 data_in [0] <= data_in [1];
204 end
205 end
206
207 //Storing the data byte at read cycle
208 always_ff #(posedge i2c_slave_scl or negedge i2c_slave_rstn) begin
209 if (!i2c_slave_rstn) begin
210 data_read <= 8'b00000000;
211 end
212 else begin
213 data_read [7] <= i2c_slave_sda_i;
214 data_read [6] <= data_read [7];
215 data_read [5] <= data_read [6];
216 data_read [4] <= data_read [5];
217 data_read [3] <= data_read [4];
218 data_read [2] <= data_read [3];
219 data_read [1] <= data_read [2];
220 data_read [0] <= data_read [1];
221 end
222 end
223
224 endmodule
The error is in these lines:
/i2c_slave.sv,169|8): Multiple drivers to always_ff output variable address_counter detected.
/i2c_slave.sv,180|8): Multiple drivers to always_ff output variable data_counter detected.

Answer 1

Variable(s) address_counter and data_counter are driven around line 51:
always_comb begin
address_counter = 0;
data_counter = 0;
Here is a 2nd driver of address_counter:
//Matching of the slave address
always_ff #(posedge i2c_slave_scl or negedge i2c_slave_rstn) begin
if (!i2c_slave_rstn) begin
address_counter <= '0; //count is 0 4 of counting the bits of slave address
end
else if (address_counter == 0) begin
addr[address_counter] <= i2c_slave_sda_i;
address_counter <= address_counter + 1;
end
end
Here is a 2nd driver of data_counter:
//Storing the register address
always_ff #(posedge i2c_slave_scl or negedge i2c_slave_rstn) begin
if (!i2c_slave_rstn) begin
data_counter <= '0;
end
else if (data_counter == 0) begin
regaddr[data_counter] <= i2c_slave_sda_i;
data_counter <= data_counter + 1;
end
end
There are two variables in the posted code which have multiple drives as the tool is indicating.
In Verilog/SV RTL synthesis workflows, the designer is modeling hardware.
When inferring multiple drivers the posted code is asking the tool to connect the outputs of two driving sources together, which is generally not possible in Verilog.
From a hardware engineering point of view, its like connecting the output of two CMOS logic gates together.
There are exceptions, however those exceptions don't apply to the posted code.
For more on multiple drivers see
https://electronics.stackexchange.com/questions/497349/is-it-possible-to-have-a-register-with-multiple-drivers
There is at least one other serious issue with the code. Variable addr is declared this way
logic [6:0] addr;
which is a single vector; its not a memory/array.
However the post refers to it as a memory/array (multiple vectors).
addr[address_counter] <= i2c_slave_sda_i;
If you want to use a memory/array, then declare the variable as a memory/array with both packed (vector) and unpacked (array) dimensions.
// a 255 location memory of 7-bit vectors
logic [6:0] addr [7:0];
The same issue exists with variable regaddr.