How to fix error [USF-XSim-62] when simulating project with Vivado Xilinx (also using DPI-C)? - simulation

Question

I have a Verilog project that makes use of a testbench written in SystemVerilog and a few imports/exports of functions through the DPI-C interface.
When attempting to simulate, I get an xsim error (as far as I can tell) and the simulation stops. I have struggled with this issue for a while, and there is no specific info given in the Vivado terminal together with the error.
The exact error received is:
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s) while executing 'path/to/proj/<proj_name>/<proj_name>.sim/sim_1/behav/xsim/elaborate.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1412.562 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
Not only is the file created by Vivado (so it should have permissions to access it), but this error appears and disappears at random. For example, modifying the testbench file and then modifying it back to original (to force recompilation) sometimes allows the simulation to run, seemingly at random.
What is even more confusing is that there are some "safe states" of the testbench code that allow the simulation to always run. My initial hunch was that it was related to the DPI-C functions, but I tried altering the files in many ways and I didn't find any obvious correlation.
Mentions
I am using Vivado 2021.2
I have implemented an automated TCL script to compile the C files using xsc and insert them into the project directory
I am using xelab command line arguments to link the C code compiled with xsc: -sv_root path/to/xsc -sv_lib dpi.
Update
When I run xelab by itself (with -v), it gives the following output (after static elaboration and simulation data flow analysis passed):
SDG Object Count: 1284, SDG Object Memory Usage: 133 KB.
Time Resolution for simulation is 1ps
Compiling package std.std
ICR Memory Usage: 491KB, 8192KB
Compiling package xil_defaultlib.$unit_tb_sv
ICR Memory Usage: 491KB, 8192KB
Compiling module xil_defaultlib.decoder_interface
ICR Memory Usage: 500KB, 8192KB
Compiling module xil_defaultlib.lut_biases
ICR Memory Usage: 584KB, 8192KB
Compiling module xil_defaultlib.saturate_default
ICR Memory Usage: 758KB, 8192KB
Compiling module xil_defaultlib.variable_nodes_default
ICR Memory Usage: 1832KB, 8192KB
Compiling module xil_defaultlib.check_nodes_default
INFO: [XSIM 43-4009] "abs_prev_proc_elem", written at line 26 in file "D:/Projects/Matlab/NN_BP_BCH/nn-min-sum-decoding/hardware/check_nodes.v", has also been read in this always_comb/always_latch block and is not added to the sensitivity list.
INFO: [XSIM 43-4009] "reg_min", written at line 30 in file "D:/Projects/Matlab/NN_BP_BCH/nn-min-sum-decoding/hardware/check_nodes.v", has also been read in this always_comb/always_latch block and is not added to the sensitivity list.
INFO: [XSIM 43-4009] "reg_sign", written at line 31 in file "D:/Projects/Matlab/NN_BP_BCH/nn-min-sum-decoding/hardware/check_nodes.v", has also been read in this always_comb/always_latch block and is not added to the sensitivity list.
INFO: [XSIM 43-4009] "temp_reg", written at line 52 in file "D:/Projects/Matlab/NN_BP_BCH/nn-min-sum-decoding/hardware/check_nodes.v", has also been read in this always_comb/always_latch block and is not added to the sensitivity list.
ICR Memory Usage: 6896KB, 8192KB
Compiling module xil_defaultlib.interm_layer
ICR Memory Usage: 6902KB, 8192KB
Compiling module xil_defaultlib.llr_to_out_default
ICR Memory Usage: 6927KB, 8192KB
Compiling module xil_defaultlib.out_layer_default
ICR Memory Usage: 7674KB, 8192KB
Compiling module xil_defaultlib.decoder_top_default
ICR Memory Usage: 8281KB, 16384KB
Compiling module xil_defaultlib.tb
child killed: unknown signal