cpu-architecture

cpu-architecture

What is the point of on-chip hardware accelerators, instead of that functionality being added as an instruction to the ISA?

Compute capability of a small (1mm^2) ASIC

Why is the Branch Target Buffer designed as a cache?

Variable allocation and RAM

RISC V manual confusion: instruction format VS immediate format

Zilog z80 I, R registers purpose

What is difference between Address Register (AR) and Program Counter register (PC)?

Finding minimum page size to allow TLB access to overlap with tag fetch [duplicate]

Do modern CPU's have compression instructions

Cache memory logic

Address translation with multiple pagesize-specific TLBs

Virtually Indexed Caches

Can Multiprocessor CPUs avoid context-switching?

Is there any case where the Bimodal will be better than Not take?

LRU Clock Replace Algorithm - What are reference bits initialized to?

Out-of-order execution vs. speculative execution

How does a computer distinguish whether a binary pattern is an instruction or just a number?

What control lines are asserted/set to 1 when a load double word instruction is called?

Is TLB used at all in the instruction fetching pipeline

Query on various addressing modes?

Instructions per second equation

Addressable memory of a CPU

Indexed addressing mode and implied addressing mode

Addressing a word inside memory frames

how cpu detect exceptions during execution?

What is the difference?

Virtually indexed virtually tagged cache

Offset in cache Mips

What is the impact of locality principles on the pipelining techniques?

Working out the maximum range of memory locations

Calculating memory stalls while adding second level cache

How critical is page size in virtual memory

what happens when address send by address register is lost before reaching the destiantion

Difference between instruction reference and data refernce

What is the total amount of virtual memory covered by one entry of page tables at each level?

When accessing memory, will the page table accessed/dirty bit be set under a cache hit situation?

I have a query related to Computer Architecture

What is the difference between quadruple multiplexer and and the regular multiplexer?

what's the difference of strong ordered architecture and poorly ordered architecture

Page table entry size - why a power of 2?

Average CPI of a processor

How does memory mapped I/O differentiate between Memory and I/O Transfer?

2 bit branch predictor with two for loops

Factors in designing Instruction set Arcitecture

Who place the data onto the cache?

can we replace Link register with program counter?

Reorder Buffer commit

Decoding RISC-V immediate (UJ-TYPE)

Execution Time of a program

How does a disassembler work and how is it different from a decompiler?

What does the gate-level circuitry of a Program Counter in a processor look like? Or the time step counter?

what is the most negative fraction that can be represented by a n bit binary number in 2's complement?

RISC-V: Immediate Encoding Variants

Does memory hierarchy implementation uses both temporal and spatial locality?

Direct Memory Access

How Jump instruction is executed based on value of Out- The Alu Output

CPU clock cycle misunderstanding

Pipeline stall after a load instruction but not after an add instruction

Branch prediction and performance

MIPS Processor I/O device support

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