Is it true that rule B should be triggered before A? Because it doesn't work for me.
rule A
salience 0
timer(int: 20s)
when
...
rule B
salience 1
timer(int: 20s)
when
...
Edit:
Conditions of the two are equal, as thus both are supposed to be triggered on the same event and condition was omitted for clearness. The point is that I would like to trigger rules after 20s timeout and make them ordinal is that possible?.
Rules with a timer are scheduled for execution as soon as the condition evaluates to true. You haven't shown the conditions for A and B, so further analysis isn't possible. It is very likely that the two timers aren't started at the very same point in time, so the expiry times can be ordered A < B. If you need B before A, run the timer for B. Add a conditional element for letting A fire without a timer and let the consequence of B insert a fact to
meet this conditional element. Roughly:
rule B
timer(int: 20s)
when...
then
insert( new TriggerForA() )
end
rule A
when
$t: TriggerForA()
...
then
delete( $t );
end
Related
i have a while loop where the condition in the while loop has two condtionals and I was wondering how pit test manged the mutations for there conditionals
while((a<=b) && (c<=d))
This would give me normally two mutants in the form of
1. changed conditional boundary → KILLED
2. changed conditional boundary → SURVIVED
I am lost as to which mutant I have killed. I believe that for the first i kill the mutant
while((a < b) && (c <=d))
I might also be wrong with the mutants and in the documentation, they don't explain in precision how they handle these cases
I want to check in my design that when signal b get asserted, then signal a should have gotten asserted 3 to 5 cycles before.
I'm looking for the different ways to check that.
Currently I'm using the following logic
sequence s_test();
##1 $rose(a) ##[3:5] 1;
endsequence
property p_test();
##1 $rose(b) |-> s_test.triggered();
Is there a way to check that property without using the sequence triggered mechanism ? I guess I could also use something like $past(a, 3) || ... || $past(a, 5), but that's cumbersome.
Also what's the difference between the sequence triggered and matched mechanism ?
We can have two approaches here: cause then effect or effect because of cause.
Cause then effect approach:
You can use a forward-time-based assertion stating that when s_test is triggered, then b should go high in 1-5 clock period of time window:
s_test.triggered |-> ##[1:5] $rose(b);
Effect then cause approach:
Alternatively, if s_test is a signal, then you can use a glue logic which monitors past 5 values of s_test. Thereafter, the assertion checks that the earlier values of s_test must have atleast 1'b1 when b rises from 0 to 1.
bit[1:5] earlier;
always #(posedge clk) begin
earlier <= {s_test, earlier[1:5]}; // shift for 5 clocks
end
p1_past20: assert property(#(posedge clk)
$rose(b) |-> $countones(earlier) >= 1);
A similar discussion is available here and a reference is over here.
You can use $past something like below.
property test_past;
#(posedge clk)
$rose(b) |-> ##[3:5] $past(a);
endproperty
triggered & matched methods differ for single clock & multi clock sequences.
Both methods show end point of a sequence, but triggered method evaluates to true if the operand sequence has reached it's end point at that particular time and false otherwise.
Whereas matched method detects endpoint of sequence, referenced in multiclocked sequence. So it provides synchronization between 2 sequences and evaluates to true after match, untill arrival of 1st clock tick of destination sequence.
triggered status of a sequence is set in observed region and is persisted through the remainder of the timestep. Whereas matched status of a sequence is set in observed region and is persisted untill the observed region of the arrival of first clock tick of destination sequence after match.
I'm new to SystemVerilog Assertions and I know that I can check if a signal doesn't change between clock ticks using Concurrent Assertions:
assert property (#(posedge clk) enable == 0 |=> $stable(data));
But how would I do so continuously using Immediate Assertions? This is an example that I found online but I'm not sure if it's what I need and how it works:
assign not_a = !a;
always_comb begin : b1
a1: assert (not_a != a);
a2: assert #0 (not_a!= a); // Should pass once values have settled
end
What you are asking for does not make any sense. If it a signal never can change, then it must be a constant. With the example you show, a1 might fail - there is a race condition between a and not_a. a2 is deferred assertion - it takes care of the race and will never fail. But the problem with both these assertions is that if a changes at some time, a2 never fails and you may are may not see a failure with a1
I need to write a rule in Drools 6.5 that checks for the existence of an event of type A. There is a second class named B which has a field date.
While checking for existence of an event A, if at least one event of type B exists, A must happen after the latest B.date in order for the rule to fire; otherwise the rule should fire regardless of any B events.
Both event types of A and B have their own explicit timestamp field.
when
// TODO if at least one event of type B exists, A must happen after max(b.date). Otherwise, the rule must fire regardless of any B
$a : A( ... )
then
...
How do I perform this check?
EDIT: If no B is present in the working memory, and A meets the requirements, the rule must fire regardless.
This will fire for each A meeting the temporal constraint that it should happen after all Bs.
$b: B()
not B(this after $b)
$a : A( this after $b )
If you want to fire this only once, for any number of As, use exists in front of A and omit the binding.
Can i only have one agenda-group declaration for the same rule in Drools 6?
Can I put this?
rule "rule_x"
agenda-group "group_x"
agenda-group "group_y"
when
then
end
I want to active a this rule when several groups are focused.
Most rule attributes are just syntactic sugar, and agenda-group is one of them. It's easy to achieve the same effect by falling back to logic patterns.
Define
class Group { private String name; ... }
and use one instance of it as a fact to represent the currently active group. Rules will have to show an additional pattern:
rule in-group-one
when
Group( name == "one" )
...
If the rule to be in several groups at the same time:
rule in-groups-one-two
when
Group( name in ("one", "two") )
You can also mimic the behaviour of agenda group stacking.
Later
The idea of focussing more than one group at the same time should be considered very carefully. While it is clear that a rule in groups a, b and c should fire when these three groups are in focus, it isn't clear at all what should happen with a rule in groups a and b, or with another rule in groups a, c and d. Whatever should happe can indeed be expressed in logic, but does it make sense, and (more importantly) is it useful?