How ID stage reads the data just being writen? [duplicate] - cpu-architecture

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Asserting Write Data for the Register File and also writing into it at the same positive clock edge ? Isn't this violating hold time conditions?
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Simultaneous reading and writing to registers
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MIPS 32-bit architecture: how can a register in a register file be read from and written to in the same clock cycle?
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Assuming that you had a MIPS processer with PIPELINE but without hazard prevention nor forwarding, would this be the correct placement of NOP?
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So this is a question about computer organization
Consider following instruciotns:
add $t2, $t2, $t2
nop
nop
add $t2, $t2, $t2
We can draw cycle diagram like:
add| IF| ID|EXE|MEM| WB|
nop| | | | | |
nop| | | | | |
add| | | | IF| ID|EXE|MEM| WB|
first add is in WB stage and second add is in ID stage.
Textbook tell me that this won't make hazard since you can write Registerfile in first half cycle and read it in second half cycle. It doesn't make sence if we assume pipeline stage and registerfile both are positive edge trigger. The behavior can described by verilog like:
always #(posedge clk)begin
if(RegWrite) regfile[waddr] <= wdata;
end
Here is the timing diagram I think:
This
As you see when second add is reading registerfile, the new data is just being written. How can you write in first half cycle when RegWrite is "LOW"?
At least there will be a clk to Q delay. It is impossible to write register at positive edge.
If clock phase of pipeline register and registerfile are different, it's not a problem anymore, but no one said that.
Or just simply tell me you can read data just being written somehow.
==============================
clk __/‾‾‾\___/‾‾‾\___
RegWrite ____/‾‾‾‾‾‾‾‾\____
there must be a clk to q delay for RegWrtie.
how Regfile write data at "clock edge" when RegWrite is LOW?

Related

How to generate a good seed

I'm looking for a method to generate a good seed for generating different series of random numbers in processes that starts at the same time.
I would like to avoid using one of the math or crypto libraries because I'm picking random numbers very frequently and my cpu resources are very limited.
I found few example for setting seeds. I tested them using the following method:
short program that picks 100 random numbers out of 5000 options. So each value has 2% chance to be selected.
run this program 100 times, so in theory, in a truly random environment, all possible values should be picked at least once.
count the number of values that were not selected at all.
This is the perl code I used. In each test I opt in only one method for generating seed:
#!/usr/bin/perl
#$seed=5432;
#$seed=(time ^ $$);
#$seed=($$ ^ unpack "%L*", `ps axww | gzip -f`);
$seed=(time ^ $$ ^ unpack "%L*", `ps axww | gzip -f`);
srand ($seed);
for ($i=0 ; $i< 100; $i++) {
printf ("%03d \n", rand (5000)+1000);
}
I ran the program 100 time and counted the values NOT selected using:
# run the program 100 times
for i in `seq 0 99`; do /tmp/rand_test.pl ; done > /tmp/list.txt
# test 1000 values (out of 5000). It should be good-enough representation.
for i in `seq 1000 1999`; do echo -n "$i "; grep -c $i /tmp/list.txt; done | grep " 0" | wc -l
The table shows the result of the tests (Lower value is better):
count Seed generation method
114 default - the line: "srand ($seed);" is commented ou
986 constant seed (5432)
122 time ^ $$
125 $$ ^ unpack "%L*", `ps axww | gzip -f`
163 time ^ $$ ^ unpack "%L*", `ps axww | gzip -f`
The constant seed method showed 986 or 1000 values not selected. In other words, only 1.4% of the possible values were selected. This is close enough to the 2% that was expected.
However, I expected that the last option that was recommended in few places, would be significantly better than the default.
Is there any better method to generate a seed for each of the processes?
I'm picking random numbers very frequently and my cpu resources are very limited.
You're worrying before you even have made a measurement.
Is there any better method to generate a seed for each of the processes?
Yes. You have to leave user space which is prone to manipulation. Simply use Crypt::URandom.
It is safe for any purpose, including fetching a seed.
It will use the kernel CSPRNG for each operating system (see source code) and hence avoid the problems shown in the article above.
It does not suffer from the documented rand weakness.
Don't generate a seed. Let Perl do it for you. Don't call srand (or call it without a parameter if you do).
Quote srand,
If srand is not called explicitly, it is called implicitly without a parameter at the first use of the rand operator
and
When called with a parameter, srand uses that for the seed; otherwise it (semi-)randomly chooses a seed.
It doesn't simply use the time as the seed.
$ perl -M5.014 -E'say for srand, srand'
2665271449
1007037147
Your goal seems to be how to generate random numbers rather than how to generate seeds. In most cases, just use a cryptographic RNG (such as Crypt::URandom in Perl) to generate the random numbers you want, rather than generate seeds for another RNG. (In general, cryptographic RNGs take care of seeding and other issues for you.) You should not use a weaker RNG unless—
the random values you generate aren't involved in information security (e.g., the random values are neither passwords nor nonces nor encryption keys), and
either—
you care about repeatable "randomness" (which is not the case here), or
you have measured the performance of your application and find random number generation to be a performance bottleneck.
Since you will generate random names for the purpose of querying a database, which may be in a remote location, it will be highly unlikely that the random number generation itself will be the performance bottleneck.

Circular Queue theory

I'm need help understanding the Circular Queue concept. I read a couple post on stackoverflow and none of the answers are answering a mental block I'm having.
For example say I have 8 cells in a Circular Queue.
Head Tail
empty|U | I | S | K | M | empty | empty
Say I insert two characters F & P, which will make the queue change to.
Tail Head
empty|U | I | S | K | M | F | P
Now lets make things interesting , what if I remove 3 entries.
Tail Head
empty| empty | empty | empty | K | M | F | P
Clearly my Head and Tail has now changed and I have 3 new available spots. But for good measures I wanted to add two more entries.
Tail Head
A| B | empty | empty | K | M | F | P
Here is my questions
Did I implement this right? LOL What happens when you fill the queue up completely as in the Tail and Head are in the same position i.e "K"? If some one can explain this concepts a little more detail and clarity I would appreciated it.
Thanks!
It looks to me like you have it right. You could make you diagram more clear by showing the integer values for head and tail
There are many explanations and examples on circular queues. I have found no better explanation than the one I posted in an answer that I offered some time ago here. It explains how head and tail show if the queue is empty, has room, or is full.
In the last row of your diagram, the queue has room for 2 more items. Adding a third would make tail = head, and would overwrite K, which you don't want to do.
When tail = head, the queue is empty. Testing for a full queue is slightly more complicated. See the link for a full explanation.
Did I implement this right?
Yes, indeed you did.
What happens when you fill the queue up completely as in the Tail and Head are in the same position i.e "K"?
K will be overwritten. This overflow condition can be checked by the condition TAIL == HEAD.
If some one can explain this concepts a little more detail and clarity I would appreciated it.
What you have to understand that in a traditional linear FIFO queue, the elements needed to be shifted continuously whenever the maximum size is reached. For example, if the queue has size of 5, then after 5 (numbers 1-5) consecutive inserts and then a delete (number 1 gets deleted), the queue becomes [null, 2, 3, 4, 5]. You can see here that although there is place for 1 more element, you cannot insert unless you shift all the elements up by one. This is why circular queue is used. It doesn't need element-shifting.
However, if your queue is constantly being overflown, the entire purpose of queue is lost. I would recommend using linked list (linear or circular) as it dynamically adds and deletes elements.
Remember that queue is used practically when there is a limitation on memory. E.g. Input/Output stream is a queue. When memory is plenty and data overriting is not prefered, linked lists are used.

use perl to extract specific output lines

I'm endeavoring to create a system to generalize rules from input text. I'm using reVerb to create my initial set of rules. Using the following command[*], for instance:
$ echo "Bananas are an excellent source of potassium." | ./reverb -q | tr '\t' '\n' | cat -n
To generate output of the form:
1 stdin
2 1
3 Bananas
4 are an excellent source of
5 potassium
6 0
7 1
8 1
9 6
10 6
11 7
12 0.9999999997341693
13 Bananas are an excellent source of potassium .
14 NNS VBP DT JJ NN IN NN .
15 B-NP B-VP B-NP I-NP I-NP I-NP I-NP O
16 bananas
17 be source of
18 potassium
I'm currently piping the output to a file, which includes the preceding white space and numbers as depicted above.
What I'm really after is just the simple rule at the end, i.e. lines 16, 17 & 18. I've been trying to create a script to extract just that component and put it to a new file in the form of a Prolog clause, i.e. be source of(banans, potassium).
Is that feasible? Can Prolog rules contain white space like that?
I think I'm locked into getting all that output from reVerb so, what would be the best way to extract the desirable component? With a Perl script? Or maybe sed?
*Later I plan to replace this with a larger input file as opposed to just single sentences.
This seems wasteful. Why not leave the tabs as they are, and use:
$ echo "Bananas are an excellent source of potassium." \
| ./reverb -q | cut --fields=16,17,18
And yes, you can have rules like this in Prolog. See the answer by #mat. You need to know a bit of Prolog before you move on, I guess.
It is easier, however, to just make the string a a valid name for a predicate:
be_source_of with underscores instead of spaces
or 'be source of' with spaces, and enclosed in single quotes.
You can use probably awk to do what you want with the three fields. See for example the printf command in awk. Or, you can parse it again from Prolog directly. Both are beyond the scope of your current question, I feel.
sed -n 'N;N
:cycle
$!{N
D
b cycle
}
s/\(.*\)\n\(.*\)\n\(.*\)/\2 (\1,\3)/p' YourFile
if number are in output and not jsut for the reference, change last sed action by
s/\^ *[0-9]\{1,\} \{1,\}\(.*\)\n *[0-9]\{1,\} \{1,\}\(.*\)\n *[0-9]\{1,\} \{1,\}\(.*\)/\2 (\1,\3)/p
assuming the last 3 lines are the source of your "rules"
Regarding the Prolog part of the question:
Yes, Prolog facts can contain whitespace like this, with suitable operator declarations present.
For example:
:- op(700, fx, be).
:- op(650, fx, source).
:- op(600, fx, of).
Example query and its result, to let you see the shape of terms that are created with this syntax:
?- write_canonical(be source of(a, b)).
be(source(of(a,b))).
Therefore, with these operator declarations, a fact like:
be source of(a, b).
is exactly the same as stating:
be(source(of(a,b)).
Depending on use cases and other definitions, it may even be an advantage to create this kind of facts (i.e., facts of the form be/1 instead of source_of/2). If this is the only kind of facts you need, you can simply write:
source_of(a, b).
This creates no redundant wrappers and is easier to use.
Or, as Boris suggested, you can use single quotes as in 'be source of'/2.

SVA - Is there any way to check an variable variable pattern in a variable length serial output using system verilog assertion?

For example, I have a pattern pt=1101 that needs to be checked in a serial output s_out= 1011101110111011 (LSB first). I am trying to check the "pt" in "s_out" only using SVA without using always block. Note: pt and s_out both are variable in length.
I am trying to use two counters for pt and s_out lengths but I don't know how to use them in SVA.
Any suggestions will be much helpful.
Thank you,
susun
You can declare internal variables in sequences and in properties. These can also have input arguments. Here's how I'd approach your problem:
First, I would create a sequence to handle matching one occurrence of the pattern. This sequence would take the pattern as an argument, together with the length:
sequence pattern_in_output(pattern, int unsigned len);
int unsigned count = 0;
(
s_out == pattern[count],
$display("time = ", $time, " count = ", count),
count += 1
) [*len];
endsequence
Notice that the pattern argument is untyped. I also left some debug prints in there for you to see how it works. Once this sequence starts, it checks for len cycles that s_out matches the appropriate bit of the pattern.
I don't know what your exact condition for checking is (when exactly you want to start and stop) so I just assumed you have a signal called tx that tells you if you are currently transmitting or not (1 means you are transmitting so we need to check, 0 means you aren't, hence no check).
The property would look something like this:
assert property (
#(posedge clk)
// check first group
$rose(tx) |-> pattern_in_output(pt, 4)
// if 'tx' is still high, need to check for another occurence
// - repeat this forever
##1 tx |-> pattern_in_output(pt, 4)
// this line causes and internal error
//##1 tx |-> pattern_in_output(pt, 4) [+] or !tx
// this prints when the property exits
##0 (1, $display("exited at ", $time))
);
We start checking on the rising edge of tx. We look for a match of our previously defined sequence. Afterwards, it could be the case that we are still transmitting and we need to check a second occurrence of the pattern. If after this second occurrence, tx is still 1, we need to check for a third and so on.
Here, I'll have to apologize for leaving you with half of an answer. I was doing this example on EDAPlayground and couldn't get this to work (I kept getting simulator internal errors). The line ##1 tx |-> pattern_in_output(pt, 4) only checks for a second occurrence. The one under that (which is commented out), ##1 tx |-> pattern_in_output(pt, 4) [+] or !tx, should check for any subsequent occurrence of the pattern while tx is still 1 and stop matching once it becomes 0.
You'll have to fiddle with the details here yourself, but I guess your question was pretty much answered. You can see how you can use internal variables inside assertion constructs.
P.S. If you want it, the full code (including testing harness) is here: http://www.edaplayground.com/x/4my

Stata mmerge update replace gives wrong output

I wanted to test what happened if I replace a variable with a different data type:
clear
input id x0
1 1
2 13
3 .
end
list
save tabA, replace
clear
input id str5 x0
1 "1"
2 "23"
3 "33"
end
list
save tabB, replace
use tabA, clear
mmerge id using tabB, type(1:1) update replace
list
The result is:
+--------------------------------------------------+
| id x0 _merge |
|--------------------------------------------------|
1. | 1 1 in both, master agrees with using data |
2. | 2 13 in both, master agrees with using data |
3. | 3 . in both, master agrees with using data |
+--------------------------------------------------+
This seems very strange to me. I expected breakdown or disagreement. Is this a bug or am I missing something?
mmerge is user-written (Jeroen Weesie, SSC, 2002).
If you use the official merge in an up-to-date Stata, you will get what you expect.
. merge 1:1 id using tabB, update replace
x0 is str5 in using data
r(106);
I have not looked inside mmerge. My own guess is that what you see is a feature from the author's point of view, namely that it's not a problem if one variable is numeric and one variable is string so long as their contents agree. But why are you not using merge directly? There was a brief period several years ago when mmerge had some advantages over merge, but that's long past. BTW, I agree in wanting my merges to be very conservative and not indulgent on variable types.